S71WS512Nx0/S71WS256Nx0 Based MCPs
Stacked Multi-chip Product (MCP)
256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with 128/64Megabit (8M/4M x 16-Bit)
pSRAM
ADVANCE
INFORMATION
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Burst Speed: 54MHz
Packages: 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
-25°C to +85°C
-40°C to +85°C
General Description
The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
One or more flash memory die
pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheet for
further details.
Flash Density
512Mb
pSRAM Density
128Mb
64Mb
32Mb
16Mb
S71WS512ND0
S71WS512NC0
256Mb
S71WS256ND0
S71WS256NC0
128Mb
64Mb
Publication Number
S71WS512/256Nx0_00
Revision
A
Amendment
0
Issue Date
October 26, 2004
A d v a n c e
I n f o r m a t i o n
S71WS512Nx0/S71WS256Nx0 Based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ................................................................................................... 1
8-, 16-, and 32-Word Linear Burst with Wrap Around ...................... 36
Table 9. Burst Address Groups ............................................ 37
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .8
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 10
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 11
CellularRAM Based Pinout . . . . . . . . . . . . . . . . . . 11
CosmoRAM Based Pinout ................................................................................ 12
Type 4 - based Pinout .........................................................................................13
MCP Look-ahead Connection Diagram ....................................................... 14
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 15
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 16
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 17
256Mb WS256N Flash + 64Mb pSRAM .........................................................17
256Mb - WS256N Flash + 128 pSRAM ..........................................................18
2x 256Mb—WS512N Flash + 64Mb pSRAM ................................................19
2x256Mb—WS256N Flash + 128Mb pSRAM ............................................. 20
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 21
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ........................................................................................... 21
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package .......................................................................................... 22
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm
MCP Compatible Package ............................................................................... 23
8-, 16-, and 32-Word Linear Burst without Wrap Around ............... 37
Configuration Register ...................................................................................... 37
RDY: Ready ...........................................................................................................37
Handshaking ......................................................................................................... 37
Simultaneous Read/Write Operations with Zero Latency ................... 38
Writing Commands/Command Sequences ................................................ 38
Unlock Bypass Mode ..................................................................................... 38
Accelerated Program/Chip Erase Operations ........................................... 38
Write Buffer Programming Operation ........................................................ 39
Autoselect Mode ................................................................................................40
Advanced Sector Protection and Unprotection ........................................41
Persistent Mode Lock Bit ..............................................................................41
Password Mode Lock Bit ..............................................................................41
Sector Protection ............................................................................................... 42
Persistent Sector Protection ........................................................................... 42
Persistent Protection Bit (PPB) .................................................................. 43
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector
Protection Mode ............................................................................................ 43
Dynamic Protection Bit (DYB) .................................................................. 43
Table 10. Sector Protection Schemes ................................... 44
Password Sector Protection ........................................................................... 45
64-bit Password .............................................................................................. 45
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector
Protection Mode ............................................................................................ 45
Lock Register .......................................................................................................46
Table 11. WS256N Lock Register ......................................... 46
Table 12. WS128N/064N Lock Register ................................. 46
S29WSxxxN MirrorBit™ Flash Family
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 24
Architectural Advantages ...........................................................................
Performance Characteristics .....................................................................
Hardware Features ......................................................................................
Security Features ..........................................................................................
Software Features .........................................................................................
Additional Features ......................................................................................
24
24
24
24
25
25
General Description 26
Product Selector Guide . . . . . . . . . . . . . . . . . . . . 29
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . .30
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 31
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 33
Table 1. Device Bus Operations ........................................... 33
Hardware Data Protection Mode .................................................................46
Write Protect (WP#) ...................................................................................46
Low V
CC
Write Inhibit ................................................................................. 47
Write Pulse “Glitch” Protection ............................................................... 47
Logical Inhibit ................................................................................................... 47
Power-Up Write Inhibit ............................................................................... 47
Standby Mode ...................................................................................................... 47
Automatic Sleep Mode ..................................................................................... 47
RESET#: Hardware Reset Input ..................................................................... 47
Output Disable Mode .......................................................................................48
SecSi™ (Secured Silicon) Sector Flash
Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Factory Locked: Factor SecSi Sector Programmed and Protected At
the Factory .......................................................................................................49
Table 13. SecSi
TM
Sector Addresses ...................................... 49
Customer SecSi Sector .................................................................................49
Common Flash Memory Interface (CFI) . . . . . . 49
Table 14. CFI Query Identification String .............................. 51
Table 15. System Interface String ........................................ 51
Table 17. Primary Vendor-Specific Extended Query ................ 52
Table 18. WS256N Sector & Memory Address Map ................. 54
Table 19. WS128N Sector & Memory Address Map ................. 62
Table 20. WS064N Sector & Memory Address Map ................. 66
VersatileIO™ (V
IO
) Control .............................................................................33
Requirements for Asynchronous (Non-Burst)
Read Operation ...................................................................................................33
Requirements for Synchronous (Burst) Read Operation .......................34
Table 2. Address Dependent Additional Latency ..................... 34
Table 3. Address Latency for 5 Wait States (≤ 68 MHz) ........... 35
Table 4. Address Latency for 4 Wait States (≤ 54 MHz) ........... 35
Table 5. Address Latency for 3 Wait States (≤ 40 MHz) ........... 35
Table 6. Address/Boundary Crossing Latency for 5 Wait States
(< 68 MHz) ...................................................................... 35
Table 7. Address/Boundary Crossing Latency for 4 Wait States
(< 54 MHz) ...................................................................... 35
Table 8. Address/Boundary Crossing Latency for 3 Wait States
(< 40 MHz) ...................................................................... 36
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 68
Reading Array Data ...........................................................................................68
Set Configuration Register Command Sequence .....................................68
Read Configuration Register Command Sequence ..................................69
Figure 1. Synchronous/Asynchronous State Diagram.............. 69
Read Mode Setting .........................................................................................69
Programmable Wait State Configuration ...............................................69
Table 21. Programmable Wait State Settings ......................... 70
Continuous Burst ............................................................................................36
Programmable Wait State ...........................................................................70
October 26, 2004 S71WS512/256Nx0_00A0
S71WS512Nx0/S71WS256Nx0
2
A d v a n c e
I n f o r m a t i o n
Boundary Crossing Latency ........................................................................ 70
Table 22. Wait States for Handshaking ................................. 70
Figure 12. CLK Characterization........................................... 98
Handshaking .................................................................................................... 70
Burst Length Configuration ........................................................................ 70
Table 23. Burst Length Configuration ................................... 71
Synchronous/Burst Read ..................................................................................99
Timing Diagrams ............................................................................................... 100
Figure 13. CLK Synchronous Burst Mode Read.....................
Figure 14. 8-word Linear Burst with Wrap Around ................
Figure 15. 8-word Linear Burst without Wrap Around ...........
Figure 16. Linear Burst with RDY Set One Cycle Before Data .
100
101
101
102
Burst Wrap Around ........................................................................................71
RDY Configuration ..........................................................................................71
RDY Polarity .....................................................................................................71
Configuration Register ...................................................................................... 72
Table 24. Configuration Register ......................................... 72
AC Characteristics—Asynchronous . . . . . . . . . . 103
Asynchronous Mode Read .............................................................................103
Timing Diagrams ................................................................................................103
Figure 17. Asynchronous Mode Read with Latched Addresses 103
Figure 18. Asynchronous Mode Read .................................. 104
Reset Command ..................................................................................................72
Autoselect Command Sequence ....................................................................73
Table 25. Autoselect Addresses ........................................... 74
Hardware Reset (RESET#) .............................................................................104
Figure 19. Reset Timings .................................................. 104
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .................74
Word Program Command Sequence ...........................................................74
Figure 2. Word Program Operation ....................................... 75
Erase/Program Timing ......................................................................................105
Figure 20. Asynchronous Program Operation Timings: WE#
Latched Addresses...........................................................
Figure 21. Synchronous Program Operation Timings:
CLK Latched Addresses ....................................................
Figure 22. Accelerated Unlock Bypass Programming Timing...
Figure 23. Data# Polling Timings
(During Embedded Algorithm)...........................................
Figure 24. Toggle Bit Timings
(During Embedded Algorithm)...........................................
Figure 25. Synchronous Data Polling Timings/
Toggle Bit Timings ...........................................................
Figure 26. DQ2 vs. DQ6 ...................................................
Figure 27. Latency with Boundary Crossing when
Frequency > 66 MHz........................................................
Figure 28. Latency with Boundary Crossing into Program/
Erase Bank .....................................................................
Figure 29. Example of Wait States Insertion........................
Figure 30. Back-to-Back Read/Write Cycle Timings ..............
106
107
108
108
109
109
110
110
111
112
113
Write Buffer Programming Command Sequence .....................................75
Table 26. Write Buffer Command Sequence .......................... 76
Figure 3. Write Buffer Programming Operation ....................... 77
Unlock Bypass Command Sequence ........................................................ 78
Chip Erase Command Sequence ................................................................... 78
Sector Erase Command Sequence ................................................................ 78
Figure 4. Erase Operation.................................................... 79
Erase Suspend/Erase Resume Commands ..................................................80
Program Suspend/Program Resume Commands ..................................... 80
Lock Register Command Set Definitions .................................................... 81
Password Protection Command Set Definitions ...................................... 81
Non-Volatile Sector Protection Command Set Definitions ................. 82
Figure 5. PPB Program/Erase Algorithm................................. 84
Global Volatile Sector Protection Freeze Command Set ..................... 85
Volatile Sector Protection Command Set .................................................. 85
SecSi Sector Entry Command ........................................................................ 86
Command Definition Summary ..................................................................... 87
Table 27. Memory Array Commands ................................... 87
Table 28. Sector Protection Commands ................................ 88
Erase and Programming Performance . . . . . . . . 114
CellularRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
General Description . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 31. Functional Block Diagram .................................. 117
Table 32. Signal Descriptions ............................................ 118
Table 33. Bus Operations—Asynchronous Mode ................... 119
Table 34. Bus Operations—Burst Mode ............................... 120
Write Operation Status . . . . . . . . . . . . . . . . . . . . .89
Figure 6. Polling Flow Chart ................................................. 89
DQ7: Data# Polling ........................................................................................... 90
DQ6: Toggle Bit I ............................................................................................... 90
DQ2: Toggle Bit II ............................................................................................... 91
Table 29. DQ6 and DQ2 Indications ..................................... 91
Reading Toggle Bits DQ6/DQ2 ..................................................................... 92
DQ5: Exceeded Timing Limits ....................................................................... 92
DQ3: Sector Erase Start Timeout State Indicator ................................... 92
DQ1: Write to Buffer Abort ............................................................................93
Table 30. Write Operation Status ......................................... 93
Functional Description . . . . . . . . . . . . . . . . . . . . 120
Power-Up Initialization ....................................................................................120
Figure 32. Power-Up Initialization Timing............................ 121
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . 121
Asynchronous Mode .........................................................................................121
Figure 33. READ Operation (ADV# LOW) ............................ 121
Figure 34. WRITE Operation (ADV# LOW)........................... 122
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .94
Figure 7. Maximum Negative Overshoot Waveform................. 94
Figure 8. Maximum Positive Overshoot Waveform .................. 94
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 94
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .95
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 9. Test Setup ........................................................... 96
Table 31. Test Specifications ............................................... 96
Page Mode READ Operation ........................................................................122
Figure 35. Page Mode READ Operation (ADV# LOW) ............ 123
Burst Mode Operation ....................................................................................123
Figure 36. Burst Mode READ (4-word burst)........................ 124
Figure 37. Burst Mode WRITE (4-word burst) ...................... 124
Key to Switching Waveforms . . . . . . . . . . . . . . . 96
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 96
Figure 10. Input Waveforms and Measurement Levels............. 96
Mixed-Mode Operation ...................................................................................125
WAIT Operation ...............................................................................................125
Figure 38. Wired or WAIT Configuration.............................. 125
LB#/UB# Operation .........................................................................................126
Figure 39. Refresh Collision During READ Operation ............. 126
Figure 40. Refresh Collision During WRITE Operation............ 127
V
CC
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
AC Characteristics—Synchronous . . . . . . . . . . . 98
CLK Characterization ....................................................................................... 98
Figure 11. V
CC
Power-up Diagram ........................................ 97
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . 127
Standby Mode Operation ................................................................................127
3
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 October 26, 2004
A d v a n c e
I n f o r m a t i o n
Temperature Compensated Refresh .......................................................... 127
Partial Array Refresh .......................................................................................128
Deep Power-Down Operation .....................................................................128
Configuration Registers . . . . . . . . . . . . . . . . . . . 128
Access Using CRE .............................................................................................128
Figure 41. Configuration Register WRITE, Asynchronous Mode
Followed by READ ............................................................ 129
Figure 42. Configuration Register WRITE, Synchronous Mode
Followed by READ0........................................................... 130
Bus Configuration Register ............................................................................ 130
Table 35. Bus Configuration Register Definition ....................131
Table 36. Sequence and Burst Length .................................132
Burst Length (BCR[2:0]): Default = Continuous Burst ..................... 132
Burst Wrap (BCR[3]): Default = No Wrap ......................................... 132
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength .............................................................................................................133
Table 37. Output Impedance .............................................133
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid ................................................................133
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH ................133
Figure 43. WAIT Configuration (BCR[8] = 0)........................ 133
Figure 44. WAIT Configuration (BCR[8] = 1)........................ 134
Figure 45. WAIT Configuration During Burst Operation .......... 134
Latency Counter (BCR[13:11]): Default = Three-Clock Latency ..... 134
Table 38. Variable Latency Configuration Codes ...................134
Figure 46. Latency Counter (Variable Initial Latency, No Refresh
Collision)......................................................................... 135
Operating Mode (BCR[15]): Default = Asynchronous Operation ..135
Refresh Configuration Register .....................................................................135
Table 39. Refresh Configuration Register Mapping ................136
Partial Array Refresh (RCR[2:0]): Default = Full Array Refresh .... 136
Table 40. 128Mb Address Patterns for PAR (RCR[4] = 1) .......136
Table 41. 64Mb Address Patterns for PAR (RCR[4] = 1) .........137
Table 42. 32Mb Address Patterns for PAR (RCR[4] = 1) .........137
Deep Power-Down (RCR[4]): Default = DPD Disabled ..................137
Temperature Compensated Refresh (RCR[6:5]): Default = +85ºC
Operation .........................................................................................................137
Page Mode Operation (RCR[7]): Default = Disabled .........................137
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 138
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 139
Table 43. Electrical Characteristics and Operating Conditions .139
Table 44. Temperature Compensated Refresh Specifications and
Conditions .......................................................................140
Table 45. Partial Array Refresh Specifications and Conditions .140
Table 46. Deep Power-Down Specifications ..........................140
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 47. AC Input/Output Reference Waveform ................. 141
Figure 48. Output Load Circuit ........................................... 141
Table 47. Output Load Circuit ............................................141
Table 48. Asynchronous READ Cycle Timing Requirements .....142
Table 49. Burst READ Cycle Timing Requirements .................143
Table 50. Asynchronous WRITE Cycle Timing Requirements ...144
Table 51. Burst WRITE Cycle Timing Requirements ...............144
Timing Diagrams ................................................................................................ 145
Figure 49. Initialization Period............................................ 145
Table 52. Initialization Timing Parameters ...........................145
Figure 50. Asynchronous READ .......................................... 146
Table 53. Asynchronous READ Timing Parameters ................146
Figure 51. Asynchronous READ Using ADV# ........................ 148
Table 54. Asynchronous READ Timing
Parameters Using ADV# ....................................................148
Figure 52. Page Mode READ............................................... 150
Table 55. Asynchronous READ Timing Parameters—Page Mode
Operation ....................................................................... 150
Figure 53. Single-Access Burst READ
Operation—Variable Latency ............................................. 152
Table 56. Burst READ Timing Parameters—Single Access, Variable
Latency .......................................................................... 152
Figure 54. Four-word Burst READ
Operation—Variable Latency ............................................. 154
Table 57. Burst READ Timing Parameters—4-word Burst ....... 155
Figure 55. Four-word Burst READ Operation (with LB#/UB#) 156
Table 58. Burst READ Timing Parameters—4-word Burst with LB#/
UB# ............................................................................... 157
Figure 56. READ Burst Suspend......................................... 158
Table 59. Burst READ Timing Parameters—Burst Suspend ..... 158
Figure 57. Continuous Burst READ Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 159
Table 60. Burst READ Timing Parameters—BCR[8] = 0 ......... 159
Figure 58. CE#-Controlled Asynchronous WRITE.................. 160
Table 61. Asynchronous WRITE Timing Parameters—CE#-
Controlled ....................................................................... 160
Figure 59. LB#/UB#-Controlled Asynchronous WRITE .......... 162
Table 62. Asynchronous WRITE Timing Parameters—LB#/UB#-
Controlled ....................................................................... 162
Figure 60. WE#-Controlled Asynchronous WRITE................. 164
Table 63. Asynchronous WRITE Timing Parameters—WE#-
Controlled ....................................................................... 164
Figure 61. Asynchronous WRITE Using ADV# ...................... 166
Table 64. Asynchronous WRITE Timing
Parameters Using ADV# ................................................... 167
Figure 62. Burst WRITE Operation ..................................... 168
Table 65. Burst WRITE Timing Parameters .......................... 169
Figure 63. Continuous Burst WRITE Showing an Output Delay with
BCR[8] = 0 for End-of-Row Condition................................. 170
Table 66. Burst WRITE Timing Parameters—BCR[8] = 0 ....... 170
Figure 64. Burst WRITE Followed by Burst READ.................. 171
Table 67. WRITE Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 171
Table 68. READ Timing Parameters—Burst WRITE Followed by
Burst READ ..................................................................... 171
Figure 65. Asynchronous WRITE Followed by Burst READ...... 172
Table 69. WRITE Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 173
Table 70. READ Timing Parameters—Asynchronous WRITE
Followed by Burst READ ................................................... 173
Figure 66. Asynchronous WRITE (ADV# LOW) Followed By Burst
READ ............................................................................. 174
Table 71. Asynchronous WRITE Timing
Parameters—ADV# LOW .................................................. 174
Table 72. Burst READ Timing Parameters ............................ 175
Figure 67. Burst READ Followed by Asynchronous WRITE (WE#-
Controlled) ..................................................................... 176
Table 73. Burst READ Timing Parameters ............................ 177
Table 74. Asynchronous WRITE Timing Parameters—WE#
Controlled ....................................................................... 177
Figure 68. Burst READ Followed by Asynchronous WRITE Using
ADV#............................................................................. 178
Table 75. Burst READ Timing Parameters ............................ 179
Table 76. Asynchronous WRITE Timing Parameters
Using ADV# .................................................................... 179
Figure 69. Asynchronous WRITE Followed by Asynchronous READ—
ADV# LOW ..................................................................... 180
Table 77. WRITE Timing Parameters—ADV# LOW ................ 180
Table 78. READ Timing Parameters—ADV# LOW .................. 181
Figure 70. Asynchronous WRITE Followed by
Asynchronous READ......................................................... 182
Table 79. WRITE Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ....................................... 182
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S71WS512Nx0/S71WS256Nx0
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A d v a n c e
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Table 80. READ Timing Parameters—Asynchronous WRITE
Followed by Asynchronous READ ........................................183
Burst Type ...........................................................................................................199
Table 90. Burst Sequence ................................................. 199
How Extended Timings Impact CellularRAM™
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Introduction ........................................................................................................ 183
Asynchronous WRITE Operation ...............................................................184
Figure 71. Extended Timing for t
CEM.............................................. 184
Figure 72. Extended Timing for t
TM................................................ 184
Table 81. Extended Cycle Impact on READ and WRITE Cycles 184
Low Power Features . . . . . . . . . . . . . . . . . . . . . 200
Internal TCSR ................................................................................................... 200
Figure 83. PAR Mode Execution and Exit ............................. 200
Table 91. PAR Mode Characteristics .................................... 200
Driver Strength Optimization ..................................................................... 200
Partial Array Refresh (PAR) mode ............................................................. 200
Extended WRITE Timing— Asynchronous WRITE Operation .....184
Figure 73. Extended WRITE Operation ................................ 185
Page Mode READ Operation ........................................................................ 185
Burst-Mode Operation .................................................................................... 185
Summary .............................................................................................................. 185
Absolute Maximum Ratings . . . . . . . . . . . . . . .
DC Recommended Operating Conditions . . . .
Capacitance (Ta = 25°C, f = 1 MHz) . . . . . . . . .
DC and Operating Characteristics . . . . . . . . . .
201
201
201
202
Common .............................................................................................................202
AC Operating Conditions . . . . . . . . . . . . . . . . . 203
Test Conditions (Test Load and Test Input/Output Reference) .......203
Figure 84. Output Load .................................................... 203
1.8V pSRAM Type 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . .
186
186
187
188
Asynchronous AC Characteristics ..............................................................204
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 205
Asynchronous Read Timing Waveform ....................................................205
Figure 85. Timing Waveform Of Asynchronous Read Cycle .... 205
Table 92. Asynchronous Read AC Characteristics ................. 205
Power Up ............................................................................................................188
Figure 74. Power Up Timing............................................... 188
Page Read .......................................................................................................206
Figure 86. Timing Waveform Of Page Read Cycle ................. 206
Table 93. Asynchronous Page Read AC Characteristics .......... 206
Standby Mode .....................................................................................................188
Figure 75. Standby Mode State Machines ............................ 188
Functional Description . . . . . . . . . . . . . . . . . . . . 189
Table 82. Asynchronous 4 Page Read & Asynchronous Write Mode
(A15/A14=0/0) ................................................................189
Table 83. Synchronous Burst Read & Asynchronous Write Mode
(A15/A14=0/1) ................................................................190
Table 84. Synchronous Burst Read & Synchronous Burst Write
Mode(A15/A14=1/0) ........................................................191
Asynchronous Write Timing Waveform ..................................................207
Figure 87. Timing Waveform Of Write Cycle ........................ 207
Table 94. Asynchronous Write AC Characteristics ................. 207
Write Cycle 2 ............................................................................................... 208
Figure 88. Timing Waveform of Write Cycle(2) .................... 208
Table 95. Asynchronous Write AC Characteristics (UB# & LB#
Controlled) ..................................................................... 208
Mode Register Setting Operation . . . . . . . . . . . . 191
Mode Register Set (MRS) ............................................................................... 192
Table 85. Mode Register Setting According to
Field of Function ...............................................................192
Table 86. Mode Register Set ..............................................193
Write Cycle (Address Latch Type) ........................................................209
Figure 89. Timing Waveform Of Write Cycle
(Address Latch Type) ....................................................... 209
Table 96. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 209
MRS Pin Control Type Mode Register Setting Timing .......................... 193
Figure 76. Mode Register Setting Timing (OE# = V
IH
) ........... 194
Table 87. MRS AC Characteristics .......................................194
Asynchronous Write Timing Waveform in Synchronous Mode ........210
Write Cycle (Low ADV# Type) ...............................................................210
Figure 90. Timing Waveform Of Write Cycle (Low ADV# Type) 210
Table 97. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 210
Asynchronous Operation . . . . . . . . . . . . . . . . . . 195
Asynchronous 4 Page Read Operation ...................................................... 195
Asynchronous Write Operation .................................................................. 195
Asynchronous Write Operation in Synchronous Mode ....................... 195
Figure 77. Asynchronous 4-Page Read ................................ 195
Figure 78. Asynchronous Write........................................... 195
Write Cycle (Low ADV# Type) ................................................................211
Figure 91. Timing Waveform Of Write Cycle (Low ADV# Type) 211
Table 98. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 211
Multiple Write Cycle (Low ADV# Type) ..............................................212
Figure 92. Timing Waveform Of Multiple Write Cycle (Low ADV#
Type)............................................................................. 212
Table 99. Asynchronous Write in Synchronous Mode AC
Characteristics ................................................................ 213
Synchronous Burst Operation . . . . . . . . . . . . . . 196
Synchronous Burst Read Operation ........................................................... 196
Synchronous Burst Write Operation ......................................................... 196
Figure 79. Synchronous Burst Read .................................... 196
Figure 80. Synchronous Burst Write.................................... 197
AC Operating Conditions . . . . . . . . . . . . . . . . . . 214
Test Conditions (Test Load and Test Input/Output Reference) ........214
Figure 93. AC Output Load Circuit...................................... 214
Table 100. Synchronous AC Characteristics ........................ 215
Synchronous Burst Operation Terminology . . 197
Clock (CLK) ........................................................................................................ 197
Latency Count .................................................................................................... 197
Table 88. Latency Count Support ........................................197
Table 89. Number of CLocks for 1st Data .............................197
Figure 81. Latency Configuration (Read) ............................. 198
Synchronous Burst Operation Timing
Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 94. Timing Waveform Of Basic Burst Operation.......... 216
Table 101. Burst Operation AC Characteristics ..................... 216
Burst Length .......................................................................................................198
Burst Stop ............................................................................................................198
Synchronous Burst Read Timing Waveform . . . 217
Read Timings .......................................................................................................217
Figure 95. Timing Waveform of Burst Read Cycle (1)............ 217
Table 102. Burst Read AC Characteristics ............................ 218
Synchronous Burst Operation Terminology . . 198
Wait Control (WAIT#) ..................................................................................198
Figure 82. WAIT# and Read/Write Latency Control ............... 199
5
S71WS512Nx0/S71WS256Nx0
S71WS512/256Nx0_00A0 October 26, 2004
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