ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC
+
16601
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
Product Features
PI74AVC
+
16601 is designed for low voltage operation,
V
CC
= 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
I
OFF
supports partial power-down operation
3.6V I/O Tolerant Inputs and Outputs
All outputs contain noise reduction circuitry reducing
noise without speed degradation
Industrial operation at 40°C to +85°C
Available Packages:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
Pericom Semiconductors PI74AVC
+
series of logic circuits are
produced using the Companys advanced sub-micron CMOS
technology, achieving industry leading speed.
The PI74AVC
+
16601 uses D-type latches and D-type flip-flops with
3-state outputs to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latch Enable (LEAB and LEBA), and Clock (CLKAB
and CLKBA) inputs. The clock can be controlled by the Clock Enable
(CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is HIGH. When LEAB
is LOW, the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the
low-to-high transition of CLKAB. Output enable OEAB is active low.
When OEAB is low, the outputs are active. When OEAB is HIGH,
the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,
CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down,
OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
Product Description
1
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ADVANCE INFORMATION
Pin Description
Pin Name
OE
CLK
Dx
Qx
GND
V
CC
Description
Output Enable Input (Active LOW)
Clock Input (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC
+
16601
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
Truth Table
(1)
†
Inputs
CLKENAB
X
X
X
H
H
L
L
OEAB LEAB
H
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
CLKAB
X
X
S
X
X
↑
↑
L OR H
A
X
L
H
X
X
L
H
X
Output
B
Z
L
H
B
0
‡
B
0
‡
L
H
B
0
‡
Pin Configuration
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
56-Pin
12
A,K
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
L
Notes:
1. H = High Signal Level
L = Low Signal Level
Z = High Impedance
↑
= LOW-to-HIGH Transition
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input
conditions were established.
2
PXXXX
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ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC
+
16601
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC ......................................................................................
0.5V to +4.6V
Input voltage range, V
I ...............................................................................................
0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, V
O(1) .........................................................
0.5V to +4.6V
Voltage range applied to any output in the
high or low state, V
O(1,2) .................................................................................
0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ........................................................................... 50mA
Output clamp current, I
OK
(V
O
<0) ..................................................................... 50mA
Continuous output current, I
O .................................................................................................
±50mA
Continuous current through each V
CC
or GND ................................................. ±100mA
Package thermal impedance,
θ
JA(3)
: package A .................................................. 64°C/W
package K ...................................................48°C/W
Storage Temperature range, T
stg ......................................................
65°C to 150°C
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Notes:
1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
(1)
M in.
V
CC
Supply Voltage
Operating
Data retention only
V
CC
= 1.2V
V
IH
High- level Input Voltage
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
CC
= 1.2V
V
IL
Low- level Input Voltage
V
CC
= 1.65V to 1.95V
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
I
V
O
Input Voltage
Output Voltage
Active State
3- State
V
CC
= 1.65V to 1.95V
I
OH
High- level output current
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
V
CC
= 1.65V to 1.95V
I
OL
Low- level output current
V
CC
= 2.3V to 2.7V
V
CC
= 3V to 3.6V
∆t∆
v Input transition rise or fall rate
T
A
Operating free- air temperature
V
CC
= 1.65V to 3.6V
40
0
0
0
1.65
1.2
V
CC
0.65 x V
CC
1.7
2
GND
0.35 x V
CC
0.7
0.8
3.6
V
CC
3.6
6
12
24
6
12
24
5
85
ns/V
°C
mA
V
M ax.
3.6
Units
Notes:
1. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
3
PXXXX
04/25/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC
+
16601
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, T
A
= -40°C
+85°C)
Parame te rs
Te s t Conditions
(1)
I
OH
= 100µA
I
OH
= 6mA
V
OH
I
OH
= 12mA
I
OH
= 24mA
V
IH
= 1.07V
V
IH
= 1.7V
V
IH
= 2V
V
CC
1.65V to 3.6V
1.65V
2.3V
3V
M in.
V
CC
0.2V
1.2
1.75
2.0
V
M ax.
Units
I
OL
= 100µA
I
OL
= 6mA
V
OL
I
OL
= 12mA
I
OL
= 24mA
I
I
Control Inputs
I
OFF
I
OZ
I
CC
Control Inputs
C
I
Data Inputs
V
I
= V
CC
or GND
V
IH
= 0.57V
V
IH
= 0.7V
V
IH
= 0.8V
1.65V to 3.6V
1.65V
2.3V
3V
3.6V
0
3.6V
3.6V
2.5V
3.3V
2.5V
3.3V
0.2
0.45
0.55
0.75
±2.5
±10
±10
40
4
4
6
6
8
8
V
I
= V
CC
or GND
V
I
or V
O
= 3.6V
V
I
= V
CC
or GND
V
O
= V
CC
or GND
I
O
= 0
µA
pF
C
O
Outputs
V
O
= V
CC
or GND
2.5V
3.3V
Note:
Typical values are measured at T
A
= 25°C.
4
PXXXX
04/25/00
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC
+
16601
2.5V 18-Bit Universal Bus Transceiver
with 3-State Outputs
Timing Requirements over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
V
CC
= 1.2V
M in
f
clock
Clock Frequency
t
w
Pulse
duration
t
su
Setup
time
LE high
CLK high or low
Data before CLK
↑
Data
before LE
↓
CLK high
CLK low
M ax
V
CC
= 1.5V
±0.1V
M in
M ax
V
CC
= 1.8V
±0.15V
M in
M ax
V
CC
= 2.5V
±0.2V
M in
3.0
3.0
2.1
1.6
1.1
1.7
0.8
1.4
1.7
0.6
M ax
180
V
CC
= 3.3V
±0.3V
M in M ax
180
3.0
3.0
1.9
1.4
0.9
1.5
0.6
1.2
1.5
0.4
Units
MHz
CLK EN before CLK
↑
Data after CLK
↑
t
h
Hold
time
Data
after LE
↓
CLK high
CLK low
ns
CLK EN after CLK
↑
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Parame te r
f
max
A or B
t
pd
LEAB or
LEBA
CLK AB or
CLK BA
t
en
t
dis
O EAB or
O EBA
A or B
B or A
From
(Input)
To
(Output)
V
CC
= 1.2V
M in
M ax
V
CC
= 1.5V
±0.1V
M in
M ax
V
CC
= 1.8V
±0.15V
M in
M ax
V
CC
= 2.5V
±0.2V
M in
180
4.1
4.7
5.0
5.2
4.4
M ax
V
CC
= 3.3V
±0.3V
M in
180
3.4
3.9
4.0
4.4
3.5
ns
M ax
MHz
Units
Operating Characteristics, T
A
= 25°C
Parame te rs
Outputs
Enabled
Outputs
Disabled
Te s t Conditions
V
CC
= 2.5V
±0.2V
Typical
Cpd Power
Dissipation
Capacitance
C
L
= 0pF,
f = 10 MHz
TBD
TBD
V
CC
= 3.3V
±0.3V
Typical
TBD
pF
TBD
Units
5
PXXXX
04/25/00
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