SMD Oscillator, PECL or LVDS
Ceramic Package, 5 mm x 7 mm
Frequency
Output Level
Level
Duty Cycle
Rise / Fall Time
Output Load
Frequency Stability
Start-up Time
Enable / Disable Time
Supply Voltage
Current
Temperature
Operating
Storage
Environmental
Package Information
1.000 MHz to 800.000 MHz
ISM99 Series
LVDS
PECL
Vod = 393 mV Typ., 475 mV Max.
‘0’ = Vcc - 1.63 V Max.
‘1’ = Vcc - 1.02 V Min.
Specify 50%
±
10% or
±
5% See Table
0.6 nS Max.
100
Ω
Differential
50
Ω
to Vcc - 2.0 VDC
See Frequency Stability Table
(Includes room temperature tolerance and stability over operating temperature)
10 mS Max.
100 nS Max.
3.3 VDC ±10%
90 mA Max.
130 mA Max.
See Operating Temperature Table
-55° C to +125° C
See Appendix B for information
MSL = N.A., Termination = e4
Tri-State Function
Pin 1 Open
Enable
Pin 1
≥
70% Vdd
Enable
Pin 1
≤
30% Vdd
Disable
Part Number Guide
Package
Input
Voltage
3 = 3.3 V
7 = 3.0 V
ISM99 -
2 = 2.7 V
6 = 2.5 V
Sample Part Number:
Operating
Temperature
1 = 0° C to +70° C
6 = -10° C to +70° C
3 = -20° C to +70° C
4 = -30° C to +75° C
2 = -40° C to +85° C
7 = 0° C to +60° C
Symmetry
(Duty Cycle)
5 = 45 / 55 Max.
6 = 40 / 60 Max.
ISM99 - 3159BH - 156.250 MHz
Output
8 = LVDS
9 = PECL
Stability
(in ppm)
*A =
±25
B =
±50
C =
±100
- 156.250 MHz
Enable /
Disable
H = Enable
Frequency
NOTE: A 0.01 µF bypass capacitor is recommended between Vcc (pin 6) and Gnd (pin 3) to minimize power supply noise.
* Not available for all temperature ranges. ** Frequency, supply, and load related parameters.
12/06
ILSI America
Phone: 775-851-8880 • Fax: 775-851-8882• e-mail: e-mail@ilsiamerica.com • www.ilsiamerica.com
Specifications subject to change without notice
D11
FPGA/CPLD
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