FDH20N40 / FDP20N40
October 2002
FDH20N40 / FDP20N40
20A, 400V, 0.216 Ohm, N-Channel SMPS Power MOSFET
Applications
Switch Mode Power Supplies(SMPS), such as
• PFC Boost
• Two-Switch Forward Converter
• Single Switch Forward Converter
• Flyback Converter
• Buck Converter
• High Speed Switching
Features
• Low Gate Charge
Requirement
Q
g
results
in
Simple
Drive
• Improved Gate, Avalanche and High Reapplied dv/dt
Ruggedness
• Reduced r
DS(ON)
• Reduced Miller Capacitance and Low Input Capacitance
• Improved Switching Speed with Low EMI
• 175°C Rated Junction Temperature
Package
JEDEC TO-247
SOURCE
DRAIN
GATE
Symbol
JEDEC TO-220AB
D
SOURCE
DRAIN
GATE
G
DRAIN
(FLANGE)
DRAIN
(FLANGE)
S
Absolute Maximum Ratings
T
C
= 25°C unless otherwise noted
Symbol
V
DSS
V
GS
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
I
D
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
=
Pulsed (Note 1)
P
D
T
J
, T
STG
Power dissipation
Derate above 25
o
C
Operating and Storage Temperature
Soldering Temperature for 10 seconds
Mounting Torque, 8-32 or M3 Screw
100
o
C,
V
GS
= 10V)
20
14
80
273
1.82
-55 to 175
300 (1.6mm from case)
10ibf*in (1.1N*m)
A
A
A
W
W/
o
C
o
o
Ratings
400
±30
Units
V
V
C
C
Thermal Characteristics
R
θJC
R
θCS
R
θJA
R
θJA
Thermal Resistance Junction to Case
Thermal Resistance Case to Sink, Flat, Greased Surface
Thermal Resistance Junction to Ambient (TO-247)
Thermal Resistance Junction to Ambient (TO-220)
0.55
0.24
40
62
o
C/W
C/W
C/W
o
C/W
o
o
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A,
FDH20N40 / FDP20N40
Package Marking and Ordering Information
Device Marking
FDH20N40
FDP20N40
Device
FDH20N40
FDP20N40
Package
TO-247
TO-220
Reel Size
Tube
Tube
Tape Width
-
-
Quantity
30
50
Electrical Characteristics
T
C
= 25°C (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Statics
B
VDSS
Drain to Source Breakdown Voltage
I
D
= 250µA, V
GS
= 0V
V/°C Reference to 25°C
I
D
= 1mA
V
GS
= 10V, I
D
= 10A
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 400V
V
GS
= 0V
V
GS
= ±20V
T
C
=
T
C
25
o
C
=150
o
C
400
-
-
2.0
-
-
-
-
0.43
0.200
3.5
-
-
-
-
-
0.216
4.0
25
250
±100
Ω
V
µA
nA
V
∆B
VDSS
/∆T
J
Breakdown Voltage Temp. Coefficient
r
DS(ON)
V
GS(th)
I
DSS
I
GSS
Drain to Source On-Resistance
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Dynamics
g
fs
Q
g(TOT)
Q
gs
Q
gd
t
d(ON)
t
r
t
d(OFF)
t
f
C
ISS
C
OSS
C
RSS
Forward Transconductance
Total Gate Charge at 10V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 50V, I
D
= 10A
V
GS
= 10V
V
DS
= 320V
I
D
= 20A
V
DD
= 200V
I
D
= 20A
R
G
= 10Ω
R
D
= 15.4Ω
V
DS
= 25V, V
GS
= 0V
f = 1MHz
10
-
-
-
-
-
-
-
-
-
-
-
35
10
12
12.4
32.5
30
34
1840
245
18
-
42
12
14.4
-
-
-
-
-
-
-
S
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
Avalanche Characteristics
E
AS
I
AR
Single Pulse Avalanche Energy (Note 2)
Avalanche Current
1100
-
-
-
-
20
mJ
A
Drain-Source Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
RR
Notes:
1:
Repetitive rating; pulse width limited by maximum junction temperature
2:
Starting T
J
= 25°C, L = 5.5mH, I
AS
= 20A
Continuous Source Current
(Body Diode)
Pulsed Source Current (Note 1)
(Body Diode)
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
MOSFET symbol
showing the
integral reverse
p-n junction diode.
I
SD
= 20A
D
-
-
-
-
-
-
-
0.9
351
4.5
20
80
1.2
456
5.85
A
A
V
ns
µC
G
S
I
SD
= 20A, dI
SD
/dt = 100A/µs
I
SD
= 20A, dI
SD
/dt = 100A/µs
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A
FDH20N40 / FDP20N40
Typical Characteristics
100
100
I
D
, DRAIN TO SOURCE CURRENT (A)
I
D
, DRAIN TO SOURCE CURRENT (A)
T
C
= 25
o
C
V
GS
DESCENDING
10V
7V
6.5V
6V
5.5V
10 5V
T
C
= 175
o
C
V
GS
DESCENDING
10V
7V
6.5V
6V
5.5V
10 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1
1
10
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 1.
Output Characteristics
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 50V
30
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
3.0
Figure 2. Output Characteristics
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
2.0
20
T
J
= 175
o
C
10
T
J
= 25
o
C
1.5
1.0
0.5
V
GS
= 10V, I
D
= 10A
0.0
-50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-25
0
25
50
75
100
125
150
175
V
GS
, GATE TO SOURCE VOLTAGE (V)
T
J
, JUNCTION TEMPERATURE (
o
C)
Figure 3. Transfer Characteristics
Figure 4. Normalized Drain To Source On
Resistance vs Junction Temperatrue
15
V
GS
, GATE TO SOURCE VOLTAGE (V)
1000
C
ISS
I
D
= 20A
C, CAPACITANCE (pF)
200V
10
80V
320V
100
C
OSS
5
10
C
RSS
V
GS
= 0V, f = 1MHz
1
1
10
100
0
0
10
20
30
40
50
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 5. Capacitance vs Drain To Source Voltage
Figure 6. Gate Charge Waveforms For Constant
Gate Current
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A
FDH20N40 / FDP20N40
Typical Characteristics
I
SD
, SOURCE TO DRAIN CURRENT (A)
40
35
100
I
D
, DRAIN CURRENT (A)
30
25
20
15
10
5
0
0.2
T
J
= 175 C
o
100µs
10
OPERATION IN THIS AREA
LIMITED BY RDS(ON)
1
1ms
10ms
DC
T
J
= 25 C
o
TC = 25
o
C
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.1
1
10
100
1000
V
SD
, SOURCE TO DRAIN VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7.
Source to Drain Diode Forward Voltage
20
Figure 8.
Maximum Safe Operating Area
I
D
, DRAIN CURRENT (A)
15
10
5
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (°C)
Figure 9. Maximum Drain Current vs Case Temperature
Z
θJC
, NORMALIZED THERMAL IMPEDANCE
2.0
1.0
0.50
0.20
0.1
0.10
P
D
0.05
0.02
0.01
0.01
10
-5
SINGLE PULSE
10
-4
10
-3
10
-2
t
2
DUTY FACTOR, D = t
1
/ t
2
PEAK T
J
= (P
D
X Z
θJC
X R
θJC
) + T
C
10
-1
10
0
t
1
t
1
, RECTANGULAR PULSE DURATION (s)
Figure 10.
Normalized Maximum Transient Thermal Impedance
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A
FDH20N40 / FDP20N40
Test Circuits and Waveforms
V
DS
t
P
L
I
AS
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
0V
R
G
-
BV
DSS
V
DS
V
DD
+
V
DD
I
AS
0.01Ω
0
t
AV
Figure 11. Unclamped Energy Test Circuit
Figure 12. Unclamped Energy Waveforms
V
DS
R
L
Q
g(TOT)
V
DS
V
GS
= 10V
V
GS
+
V
DD
-
DUT
I
g(REF)
0
V
GS
V
GS
= 1V
Q
g(TH)
Q
gs
I
g(REF)
0
Q
gd
Figure 13. Gate Charge Test Circuit
Figure 14. Gate Charge Waveforms
V
DS
t
ON
t
d(ON)
R
L
V
DS
90%
t
r
t
OFF
t
d(OFF)
t
f
90%
V
GS
+
V
DD
-
DUT
0
10%
10%
90%
V
GS
50%
PULSE WIDTH
50%
R
GS
V
GS
0
10%
Figure 15. Switching Time Test Circuit
Figure 16. Switching Time Waveform
©2002 Fairchild Semiconductor Corporation
FDH20N40 / FDP20N40 Rev. A
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