TN0108
Technical note
Migration differences between SPC560B4x/50 and
SPC560C4x/50 512KB Cut 1 to Cut 2
Introduction
STMicroelectronics have created an e200Z0 core-based Power Architecture family of
devices targeted at automotive body applications.
This document details the changes that have been implemented going between Cut 1.1 and
Cut 2 of the device.
Reading this document will expedite migration time for customers, who are currently using
Cut 1.1 silicon and will require to migrate to the Cut 2 device.
This document is not intended to replace the reference manual or device errata list and
differences pointed out in this document should be cross referenced with the relevant
sections in the latest reference manual and errata document.
The
Table 1
shows the full part numbers and device identification.
Table 1.
Device identification
Maskset
Part numbers
Cut 1.1
SPC560B40L3,
SPC560B40L5,
SPC560B44L3,
SPC560B44L5,
SPC560B50B2,
STMicroelectronics
SPC560B50L3,
SPC560B50L5,
SPC560C40L3,
SPC560C44L3,
SPC560C50L3
Cut 2
Cut 1.1
Cut 2
JTAG ID
Package device
marking mask
identifier
Cut 1.1
Cut 2
Device
manufacturer
FB50X11Z
FB50X20B 0x1AE40041 0x0AE41041
Z
B
For simplicity throughout this document, the MCU will be referred to as the SPC560B. For
differences between the B and C variants, please consult the reference manual.
September 2013
Doc ID 15874 Rev 2
1/26
www.st.com
Contents
TN0108
Contents
1
2
Summary of differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory and memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
SRAM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
3.4
Additional GPIO on JTAG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Medium speed pad allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/output state during and after reset . . . . . . . . . . . . . . . . . . . . . . . . . . 9
GPIO pin configuration in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
4.3
Debug through LPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
JTAG operation in safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Nexus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
Peripheral clock prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC register map change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ADC additional external result registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ADC multiplex control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC clock prescaler divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC abort modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ADC offset calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LINFlex slave configuration change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LINFlex slave filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
eMIOS additional modes and channel types . . . . . . . . . . . . . . . . . . . . . . 15
6
Reset and BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
6.2
6.3
Reset Configuration Halfword (RCHW) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Correct reset event-disable feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write once protection of reset configuration registers . . . . . . . . . . . . . . . 18
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6.4
Unused BAM space abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Clocks (including RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1
7.2
7.3
7.4
Invalid clock selection inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RTC counter updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RTC operation through non-destructive reset . . . . . . . . . . . . . . . . . . . . . 21
External 32 kHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
CTU (Cross Triggering Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1
8.2
CTU source update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CTU PIT/eMIOS configuration change . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Power, low power, and wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1
9.2
9.3
9.4
API/RTC wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Halt mode defect fixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standby mode exit Flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Voltage regulator power up current clamping . . . . . . . . . . . . . . . . . . . . . . 23
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of tables
TN0108
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Summary of differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SRAM size differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
JTAG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Additional medium speed pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I/O state during and after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
JTAG pins SMC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RGM_DERD and RGM_FERD write-once protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MA[0..2] pad multiplexing locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ADC conversion chain abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LINFlex configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LINFlex slave filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
eMIOS modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RCHW differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset event disable via RGM_DERD and RGM_FERD . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RGM_DERD and RGM_FERD write-once protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Unclocked peripheral behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RTC operation through non-destructive reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Additional CTU sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CTU PIT trigger source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Wakeup sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standby mode exit Flash control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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TN0108
Summary of differences
1
Summary of differences
This section gives a summary of all the differences between the SPC560B 512 KB Flash
size silicon revisions Cut 1.1 and Cut 2. These differences are described in more detail in
the following sections. For ease of navigation, the section number provides a link to the
appropriate section.
Table 2.
Summary of differences
Description
Cut 1.1
32 KB SRAM
Dedicated JTAG pins
Cut 2
48 KB SRAM
Added PH[9] and PH[10] to
TMS and TCK
27 additional medium pads
High-Z in reset, then input
with weak pull-up
Not supported
High-Z during and after reset
except JTAG and ABS pins
Supported
Section
Section 2.1
Section 3.1
Section 3.2
Section 3.3
Section 4.1
Section 4.2
Section 4.3
Section 5.1
Section 5.2
Section 5.3
Section 5.4
Section 5.5
Section 5.6
Section 5.7
Section 5.8
Section 5.9
Section 5.10
Section 6.1
Section 6.2
Section 6.3
SRAM size increase
Additional GPIO on JTAG pins
Medium speed pad allocation
GPIO state during and after reset
Debug through LPM
JTAG operation in safe mode
Nexus TAP change
Peripheral clock prescalers
ADC register map change
ADC additional external result
register
ADC multiplex control
ADC clock prescaler divider
ADC abort
ADC offset calculation
LINFlex configuration change
LINFlex slave filters
eMIOS additional modes and
channel types
RCHW format
Correct reset event disable
Protection of reset event disable
registers
JTAG pins tri-state by default SMC modified, so JTAG pins
in SAFE mode
remain active in SAFE mode
Change to TAP command
Disabled out of reset
Enabled out of reset
Fundamentally different to
Cut 2. Code change required.
Four external results
registers for ANX[0..3]
32 external results registers
covering full external mux
Additional pad-multiplexing
options.
Set to sysclk/2
Slow abort for chained
commands
Implemented
All four LINFlex modules
support master/slave
Eight ID filters on LINFlex0
Eight modes and three
channel types
0x0000_005A
Option to use sysclk/2 when in
LPM on 16 MHz IRC
New “abortchain” control bit
added for rapid abort.
Removed. Did not provide any
benefit to ADC precision.
LINFlex 0 is master /slave, all
others are master only
16 ID filters on LINFlex0
Added two more channel
types with four more modes
0x005A_0000
Can disable all reset sources Allow ability to lock all reset
in DERD/FERD
config registers
Write-once protection based
on 32-bit resolution
Individual 16-bit protection for
DERD/FERD
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