Datasheet
μ
PD44324092B
μ
PD44324182B
μ
PD44324362B
36M-BIT DDR II SRAM
2-WORD BURST OPERATION
Description
The
μ
PD44324092B is a 4,194,304-word by 9-bit, the
μ
PD44324182B is a 2,097,152-word by 18-bit and the
μ
PD44324362B is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44324092B,
μ
PD44324182B and
μ
PD44324362B integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the
positive edge of K and K#. These products are suitable for application which require synchronous operation,
high speed, low voltage, high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
R10DS0036EJ0200
Rev.2.00
August 2, 2011
Features
•
1.8
±
0.1 V power supply
•
165-pin PLASTIC BGA (15 x 17)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Pipelined double data rate operation
•
Common data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 3.5ns (287MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0036EJ0100 Rev.2.00
August 2, 2011
Page 1 of 36
μ
PD44324092B,
μ
PD44324182B,
μ
PD44324362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44324092B]
4M x 9
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
NC
DQ5
NC
DQ6
V
DD
Q
NC
NC
NC
NC
NC
DQ8
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC/288M
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
DQ0 to DQ8
LD#
R, W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
2.
3.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 4 of 36
μ
PD44324092B,
μ
PD44324182B,
μ
PD44324362B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44324182B]
2M x 18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DD
Q
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC/288M
6
K#
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A0, A
DQ0 to DQ17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
2.
3.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 7A and 5B are expansion addresses : 2A for 72Mb
: 2A and 7A for 144Mb
: 2A, 7A and 5B for 288Mb
2A of this product can also be used as NC.
R10DS0036EJ0200 Rev.2.00
August 2, 2011
Page 5 of 36
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