Package Type E and Q . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
Storage Temperature Range (T
STG
) . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering)
At distance 1/16
±
1/32 In. (1.59
±
0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
At T
A
= -40 to +85
o
C. For maximum reliability, operating conditions should be selected
so that operation is always within the following ranges:
LIMITS
CDP1871AD, CDP1871AE
CDP1871ACD, CDP1871ACE
MIN
4
V
SS
MAX
6.5
V
DD
UNITS
V
V
PARAMETER
Supply Voltage Range
Recommended Input Voltage
Range
Clock Input Frequency, TPB
(Keyboard Capacitance = 200 pF)
f
CL
V
DD
(V)
MIN
4
V
SS
MAX
10.5
V
DD
5
10
DC
DC
0.4
0.8
DC
-
0.4
-
MHz
MHz
NOTE:
1. Printed-circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
Static Electrical Specifications
At T
A
= -40 to +85
o
C, Unless Otherwise Specified
CONDITIONS
CDP1871AD
CDP1871AE
V
O
(V)
V
IN
(V)
0.5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
V
DD
(V)
5
10
5
10
5
10
5
10
(NOTE 1)
TYP
0.1
1
1
2
1.5
2
0.1
0.2
LIMITS
CDP1871ACD
CDP1871ACE
(NOTE1)
TYP
1
-
1
-
1.5
-
0.1
-
PARAMETER
Quiescent Device
Current
I
DD
MIN
-
-
0.5
1
0.75
1
0.05
0.1
MAX
50
200
-
-
-
-
-
-
MIN
-
-
0.5
-
0.75
-
0.05
-
MAX
200
-
-
-
-
-
-
-
UNITS
µA
µA
mA
mA
mA
mA
mA
mA
-
-
Output Low Drive (Sink)
Current (Except Debounce
and D1-D11)
Debounce
I
OL
0.4
0.5
I
OL
0.4
0.5
D1-D11
I
OL
0.4
0.5
4-68
CDP1871A, CDP1871ACCDP1871A, CDP1871AC
Static Electrical Specifications
At T
A
= -40 to +85
o
C, Unless Otherwise Specified
(Continued)
CONDITIONS
CDP1871AD
CDP1871AE
V
O
(V)
I
OH
4.6
9.5
Input Low Voltage
(Except Debounce)
V
IL
0.5, 4.5
1, 9
Input High Voltage
(Except Debounce)
V
IH
0.5, 4.5
1, 9
Debounce Schmitt Trigger
Input Voltage
Positive Trigger Voltage
Negative Trigger Voltage
V
N
V
D
0.4
V
IN
(V)
0, 5
0, 10
-
-
-
-
-
V
DD
(V)
5
10
5
10
5
10
5
(NOTE 1)
TYP
-0.6
-1.5
-
-
-
-
3.3
LIMITS
CDP1871ACD
CDP1871ACE
(NOTE1)
TYP
-0.6
-
-
-
-
-
3.3
PARAMETER
Output High Drive (Source)
Current
MIN
-0.3
-0.75
-
-
3.5
7
2.0
MAX
-
-
1.5
3
-
-
4.0
MIN
-0.3
-
-
-
3.5
-
2.0
MAX
-
-
1.5
-
-
-
4.0
UNITS
mA
mA
V
V
V
V
V
0.5
0.4
0.5
-
-
-
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
10
5
10
5
10
5
10
5
10
5
10
5
10
-
4.0
0.8
1.9
0.3
0.7
-
-
4.95
9.95
-
-
-
-
7
6.3
1.8
4.0
1.6
2.3
0
0
5
10
0.01
0.01
0.01
0.02
14
8.0
3.0
6.0
2.6
4.7
0.05
0.05
-
-
1
1
1
2
24
-
0.8
-
0.3
-
-
-
4.95
-
-
-
-
-
7
-
1.8
-
1.6
-
0
-
5
-
0.01
-
0.02
-
14
-
3.0
-
2.6
-
0.05
-
-
-
1
-
2
-
24
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
kΩ
Hysteresis
V
H
0.4
0.5
Output Voltage Low Level
V
OL
-
-
Output Voltage High Level
V
OH
-
-
Input Leakage Current
(Except S1-S8, Shift,
Control)
Three-State Output Leakage
Current
I
IN
-
-
I
OUT
0, 5
0, 10
Pull-Down Resistor Value
(S1-S8, Shift, Control)
Operating Current
(All Outputs Unloaded)
f
CL
= 0.4MHz
f
CL
= 0.8MHz
NOTE:
R
PD
-
I
OPER
0.5, 4.5
1, 9
0, 5
0, 10
5
10
-
-
0.6
2.7
-
-
-
-
0.6
-
-
-
mA
mA
1. Typical values are for T
A
= +25
o
C and nominal V
DD
.
4-69
CDP1871A, CDP1871AC
Functional Description of
CDP1871A Terminals
D1 - D11 (Outputs):
Drive lines for the 11 x 8 keyboard switch matrix. These
outputs are connected through the external switch matrix to
the sense lines (S1 - S8).
S1 - S8 (Inputs):
Sense lines for the 11 x 8 keyboard maxtrix. These inputs
have internal pull-down resistors and are driven high by
appropriate drive line when a keyboard switch is closed.
CS1, CS2, CS3, CS4 (Inputs):
Chip select inputs, which are used to enable the three-state
data bus outputs (BUS 0 - BUS 7) and to enable the reset-
ting of the status flag (DA), which occurs on the low-to-high
transition of TPB. These four inputs are normally connected
to the N-lines (N0-N2) and MRD output of the CDP1800-
series microprocessor. (Table 2)
BUS 0 - BUS 7 (Outputs):
Three-state data bus outputs which provide the ASCll and
HEX codes of the detected keys. The outputs are normally
connected to the BUS 0 - BUS 7 terminals of the CDP1800-
series microprocessor.
DA (Output):
The data available output flag which is set low when a valid
key closure is detected. It is reset high by the low-to-high
transition of TPB when data is read from the CDP1871A.
This output is normally connected to a flag input (EF1 - EF4)
of the CDP1800-series microprocessor.
ALPHA, SHIFT, CONTROL (Inputs):
A high on the SHIFT or CONTROL inputs will be internally
latched (after the debounce time) and the drive and sense
line decoding will be modified as shown in Table 3. They are
normally connected to the keyboard, but produce no code by
themselves. The SHIFT and CONTROL inputs have internal
pull-down resistors to simplify use with momentary contact
switches. The ALPHA input is not latched and is designed for
a standard SPDT switch to provide an alpha-lock function.
When ALPHA = 1 the drive and sense line decoding will be
modified as shown in Table 3.
V
DD
, V
SS
:
V
DD
is the positive supply voltage input. V
SS
is the most
negative supply voltage terminal and is normal connected to
ground. All outputs swing from V
SS
to V
DD
. The
recommended input voltage swing is from V
SS
to V
DD
.
TABLE 1. SWITCH INPUT FUNCTIONS
CONTROL
0
1
0
0
NOTE:
X = Don’t Care
SHIFT
0
X
1
0
ALPHA
0
X
X
1
KEY FUNCTION
Normal
Control
Shift
Alpha
TPB (Input):
The input clock used to drive the scan generator and reset
the status flag (DA). This input is normally connected to the
TPB output of the CDP1800-series microprocessor.
RPT (Output):
The repeat output flag which is used to indicate that a key is
still closed after data has been read from the CDP1871A
(DA = high). It remains low as long as the key is closed and
is used for an autorepeat function, under CPU control. This
output is normally connected to a flag input (EF1 - EF4) of
the CDP1800-series microprocessor.
DEBOUNCE (Input):
This input is connected to the junction of an external resistor
to V
DD
and capacitor to V
SS
. It provides a debounce time
delay (t
≅
RC) after the release of a key. If a debounce is not
desired, the external pull-up resistor is still required.
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