W9816G6JB datasheet, PDF - EEWORLD Datasheet

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W9816G6JB: Description512K X 2 BANKS X 16 BITS SDRAM; File Size1MB，42 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W9816G6JB Overview

512K X 2 BANKS X 16 BITS SDRAM

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W9816G6JB

512K



2 BANKS



16 BITS SDRAM

Table of Contents-

GENERAL DESCRIPTION ......................................................................................................... 3

FEATURES ................................................................................................................................. 3

ORDER INFORMATION ............................................................................................................. 4

BALL CONFIGURATION ............................................................................................................ 4

BALL DESCRIPTION .................................................................................................................. 5

BLOCK DIAGRAM ...................................................................................................................... 6

FUNCTIONAL DESCRIPTION.................................................................................................... 7

7.1

Power Up and Initialization ............................................................................................. 7

7.2

Programming Mode Register .......................................................................................... 7

7.3

Bank Activate Command ................................................................................................ 7

7.4

Read and Write Access Modes ...................................................................................... 7

7.5

Burst Read Command .................................................................................................... 8

7.6

Burst Write Command .................................................................................................... 8

7.7

Read Interrupted by a Read ........................................................................................... 8

7.8

Read Interrupted by a Write ............................................................................................ 8

7.9

Write Interrupted by a Write ............................................................................................ 8

7.10 Write Interrupted by a Read ............................................................................................ 8

7.11 Burst Stop Command ..................................................................................................... 9

7.12 Addressing Sequence of Sequential Mode .................................................................... 9

7.13 Addressing Sequence of Interleave Mode ...................................................................... 9

7.14 Auto-precharge Command ........................................................................................... 10

7.15 Precharge Command .................................................................................................... 10

7.16 Self Refresh Command ................................................................................................ 10

7.17 Power Down Mode ....................................................................................................... 11

7.18 No Operation Command ............................................................................................... 11

7.19 Deselect Command ...................................................................................................... 11

7.20 Clock Suspend Mode .................................................................................................... 11

OPERATION MODE ................................................................................................................. 12

ELECTRICAL CHARACTERISTICS ......................................................................................... 13

9.1

Absolute Maximum Ratings .......................................................................................... 13

9.2

Recommended DC Operating Conditions .................................................................... 13

9.3

Capacitance .................................................................................................................. 13

9.4

DC Characteristics ........................................................................................................ 14

9.5

AC Characteristics ........................................................................................................ 15

TIMING WAVEFORMS ............................................................................................................. 17

10.1 Command Input Timing ................................................................................................ 17

10.2 Read Timing.................................................................................................................. 18

10.3 Control Timing of Input/Output Data ............................................................................. 19

10.4 Mode Register Set Cycle .............................................................................................. 20

OPERATING TIMING EXAMPLE ............................................................................................. 21

10.

11.

-1-

Publication Release Date: Mar. 01, 2017

Revision: A01

W9816G6JB

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 21

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 22

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 23

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 24

11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 25

11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 27

11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ................................... 28

11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 29

11.10 Auto Precharge Write (Burst Length = 4) .................................................................... 30

11.11 Auto Refresh Cycle ..................................................................................................... 31

11.12 Self Refresh Cycle ....................................................................................................... 32

11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 33

11.14 Power Down Mode ...................................................................................................... 34

11.15 Auto-precharge Timing (Read Cycle) .......................................................................... 35

11.16 Auto-precharge Timing (Write Cycle) .......................................................................... 36

11.17 Timing Chart of Read to Write Cycle ........................................................................... 37

11.18 Timing Chart of Write to Read Cycle ........................................................................... 37

11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 38

11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 38

11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 39

11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 40

PACKAGE SPECIFICATION .................................................................................................... 41

REVISION HISTORY ................................................................................................................ 42

12.

13.

-2-

Publication Release Date: Mar. 01, 2017

Revision: A01

W9816G6JB

1. GENERAL DESCRIPTION

W9816G6JB is a high-speed synchronous dynamic random access memory (SDRAM), organized as

512K words



2 banks



16 bits. W9816G6JB delivers a data bandwidth of up to 200M words per

second. To fully comply with the personal computer industrial standard, W9816G6JB is sorted into the

following speed grades: -5, -6, -6I, -7 and -7I.

The -5 grade parts can run up to 200MHz/CL3.

The -6 and -6I grade parts can run up to 166MHz/CL3 (the -6I industrial grade parts which is

guaranteed to support -40°C ≤ T

≤ 85°C).

The -7 and -7I grade parts can run up to 143MHz/CL3 (the -7I industrial grade parts which is

guaranteed to support -40°C ≤ T

≤ 85°C).

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle. The

multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W9816G6JB is ideal for main memory in

high performance applications.

2. FEATURES



3.3V ± 0.3V power supply for -5/-6/-6I speed grades

2.7V~3.6V power supply for -7/-7I speed grades

Up to 200 MHz Clock Frequency

524,288 words x 2 banks x 16 bits organization

Self Refresh current: standard and low power

CAS Latency: 2 and 3

Burst Length: 1, 2, 4, 8 and Full Page

Burst Read, Single Writes Mode

Byte Data Controlled by LDQM, UDQM

Auto-precharge and Controlled Precharge

2K Refresh Cycles/32 mS

Interface: LVTTL

Packaged in VFBGA 60 balls pitch=0.65mm, using Lead free materials with RoHS compliant

-3-

Publication Release Date: Mar. 01, 2017

Revision: A01

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Description	512K X 2 BANKS X 16 BITS SDRAM	512K X 2 BANKS X 16 BITS SDRAM	512K X 2 BANKS X 16 BITS SDRAM	512K X 2 BANKS X 16 BITS SDRAM	512K X 2 BANKS X 16 BITS SDRAM	512K X 2 BANKS X 16 BITS SDRAM

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