Class-D Audio Power Amplifier
ADAU1592
FEATURES
Integrated stereo modulator and power stage
0.005% THD + N
101 dB dynamic range
PSRR > 65 dB
R
DS-ON
< 0.3 Ω (per transistor)
Efficiency > 90% (8 Ω)
EMI-optimized modulator
On/off-mute pop-noise suppression
Short-circuit protection
Overtemperature protection
GENERAL DESCRIPTION
The ADAU1592 is a 2-channel, bridge-tied load (BTL)
switching audio power amplifier with an integrated Σ-Δ
modulator.
The modulator accepts an analog input signal and generates
a switching output to drive speakers directly. A digital,
microcontroller-compatible interface provides control of reset,
mute, and PGA gain as well as output signals for thermal and
overcurrent error conditions. The output stage can operate
from supply voltages ranging from 9 V to 18 V. The analog
modulator and digital logic operate from a 3.3 V supply.
APPLICATIONS
Flat panel televisions
PC audio systems
Mini-components
FUNCTIONAL BLOCK DIAGRAM
PGA0
PGA1
PVDD
AINL
PGA
A1
A2
OUTL+
PGND
PVDD
B1
SLC_TH
SLICER
Σ-Δ
MODULATOR
B2
OUTL–
PGND
PVDD
C1
C2
AINR
PGA
OUTR+
PGND
PVDD
PGA0
AVDD
PGA1
D1
D2
OUTR–
PGND
LEVEL SHIFT
AND DEAD
TIME CONTROL
VREF
AGND
DVDD
DGND
VOLTAGE
REFERENCE
f
CLK
/2
CLOCK
OSCILLATOR
MODE CONTROL
LOGIC
TEMPERATURE/
OVERCURRENT
PROTECTION
XTI
XTO MO/ST STDN MUTE ERR OTW
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
06749-001
ADAU1592
ADAU1592
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Audio Performance ...................................................................... 3
DC Specifications ......................................................................... 4
Power Supplies .............................................................................. 4
Digital I/O ..................................................................................... 4
Digital Timing............................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 15
Overview...................................................................................... 15
Modulator.................................................................................... 15
Slicer ............................................................................................. 15
Power Stage ................................................................................. 16
Gain.............................................................................................. 16
Protection Circuits ..................................................................... 16
Thermal Protection.................................................................... 16
Overcurrent Protection ............................................................. 16
Undervoltage Protection ........................................................... 17
Clock Loss Detection ................................................................. 17
Automatic Recovery from Protections .................................... 17
MUTE and STDN ...................................................................... 17
Power-Up/Power-Down Sequence .......................................... 18
DC Offset and Pop Noise .......................................................... 19
Selecting Values for C
REF
and C
IN
.............................................. 19
Mono Mode................................................................................. 19
Power Supply Decoupling ......................................................... 19
External Protection for PVDD > 15 V .................................... 20
Clock ............................................................................................ 20
Applications Information .............................................................. 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
9/07—Rev. 0 to Rev. A
Changes to Figure 14, Figure 15, and Figure 16 ......................... 10
Changes to Applications Information Section............................ 21
Changes to Ordering Guide .......................................................... 23
5/07—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADAU1592
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 3.3 V, PVDD = 15 V, ambient temperature = 25°C, load impedance = 6 Ω, clock frequency = 24.576 MHz,
measurement bandwidth = 20 Hz to 20 kHz, unless otherwise specified.
AUDIO PERFORMANCE
Table 1.
Parameter
OUTPUT POWER
1
Min
Typ
12
15
14.5
18
19.5
24
87
0.28
0.25
135
150
6
5.1
1.0
0.5
0.25
0.125
0.005
101
101
−90
19
25
31
37
78
100
158
280
65
Max
Unit
W
W
W
W
W
W
%
Ω
Ω
°C
°C
A
V
V
rms
V
rms
V
rms
V
rms
%
dB
dB
dB
dB
dB
dB
dB
PVDD = 15 V, 6 Ω
μV
μV
μV
μV
dB
Test Conditions/Comments
1 kHz
1% THD + N, 8 Ω
10% THD + N, 8 Ω
1% THD + N, 6 Ω
10% THD + N, 6 Ω
1% THD + N, 4 Ω
10% THD + N, 4 Ω
@ 18 W, 6 Ω
@ T
CASE
= 25°C
@ 100 mA
@ 100 mA
Die temperature
Die temperature
Peak current
Full-scale output @ 1% THD + N
PGA gain = 0 dB
PGA gain = 6 dB
PGA gain = 12 dB
PGA gain = 18 dB
1 kHz, P
OUT
= 1 W, PGA gain = 0 dB
A-weighted, referred to 1% THD + N output
A-weighted, measured with −60 dBFS input
@ full-scale output voltage, 1% THD + N, 1 kHz
PVDD = 15 V, 6 Ω
EFFICIENCY
R
DS-ON
Per High-Side Transistor
Per Low-Side Transistor
THERMAL CHARACTERISTICS
Thermal Warning Active
2
Thermal Shutdown Active
OVERCURRENT SHUTDOWN ACTIVE
PVDD UNDERVOLTAGE SHUTDOWN
INPUT LEVEL FOR FULL-SCALE OUTPUT
5
TOTAL HARMONIC DISTORTION + NOISE (THD + N)
SIGNAL-TO-NOISE RATIO (SNR)
DYNAMIC RANGE (DNR)
CROSSTALK (LEFT TO RIGHT OR RIGHT TO LEFT)
AMPLIFIER GAIN
PGA = 0 dB
PGA = 6 dB
PGA = 12 dB
PGA = 18 dB
OUTPUT NOISE VOLTAGE
PGA = 0 dB
PGA = 6 dB
PGA = 12 dB
PGA = 18 dB
POWER SUPPLY REJECTION RATIO (PSRR)
1
2
99
99
20 Hz to 20 kHz, 1.5 V p-p ripple, inputs
ac-coupled to AGND
Output powers above 12 W at 4 Ω and above 18 W at 6 Ω are not continuous and are thermally limited by the package dissipation.
Thermal warning flag is for indication of device T
J
reaching close to shutdown temperature.
Rev. A | Page 3 of 24
ADAU1592
DC SPECIFICATIONS
Table 2.
Parameter
INPUT IMPEDANCE
OUTPUT DC OFFSET VOLTAGE
Min
Typ
20
±3
Max
Unit
kΩ
mV
Test Conditions/Comments
AINL/AINR
POWER SUPPLIES
Table 3.
Parameter
ANALOG SUPPLY VOLTAGE (AVDD)
DIGITAL SUPPLY VOLTAGE (DVDD)
POWER TRANSISTOR SUPPLY VOLTAGE (PVDD)
POWER-DOWN CURRENT
AVDD
DVDD
PVDD
MUTE CURRENT
AVDD
DVDD
PVDD
OPERATING CURRENT
AVDD
DVDD
PVDD
Min
3.0
3.0
9
Typ
3.3
3.3
15
5
0.1
0.082
13
1.7
5.4
13
2.7
44
Max
3.6
3.6
18
60
0.24
0.25
20
3.2
8
30
4
65
Unit
V
V
V
μA
mA
mA
MUTE held low
mA
mA
mA
STDN and MUTE held high, no input
mA
mA
mA
Test Conditions/Comments
STDN held low
DIGITAL I/O
Table 4.
Parameter
INPUT VOLTAGE
Input Voltage High
Input Voltage Low
OUTPUT VOLTAGE
Output Voltage High
Output Voltage Low
LEAKAGE CURRENT ON DIGITAL INPUTS
Min
2
0.8
2
0.4
10
Typ
Max
Unit
V
V
V
V
μA
@ 2 mA
@ 2 mA
Test Conditions/Comments
Rev. A | Page 4 of 24
ADAU1592
DIGITAL TIMING
Table 5.
Parameter
t
WAIT
t
INT
t
HOLD
t
OUTx+/OUTx− SW
t
OUTx+/OUTx− MUTE
1
2
Min
0.01
1
10
1
Typ
1000
2
650
250
3
200
200
Unit
ms
ms
μs
μs
μs
Test Conditions/Comments
Wait time for unmute
Internal mute time
Wait time for shutdown
Time delay after MUTE held high until output starts switching
Time delay after MUTE held low until output stops switching
t
WAIT MIN
and t
HOLD MIN
are the minimum times for fast turn-on and do not guarantee pop-and-click suppression.
t
WAIT TYP
is the recommended value for minimum pop and click during the unmute of the amplifier. The recommended value is 1 sec. It is calculated using the input
coupling capacitor value and the input resistance of the device. See the Power-Up/Power-Down Sequence section.
3
t
HOLD TYP
is the recommended value for minimum pop and click during the mute of the amplifier.
STDN
INTERNAL MUTE
t
INT
t
HOLD MIN
t
WAIT MIN
MUTE
OUTx+/OUTx–
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
06749-002
Figure 2. Timing Diagram (Minimum)
STDN
INTERNAL MUTE
MUTE
OUTx+/OUTx–
t
INT
t
HOLD TYP
t
WAIT TYP
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
Figure 3. Timing Diagram (Typical)
Rev. A | Page 5 of 24
06749-003
t
OUTx+/OUTx– SW
t
OUTx+/OUTx– MUTE
京公网安备 11010802033920号
EEWORLD
