LC89515 datasheet, PDF - EEWORLD Datasheet

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LC89515: DescriptionCD-ROM/CD-I Error Correction/ Host Interface LSI; File Size48KB，6 Pages; ManufacturerSANYO; Websitehttp://www.semic.sanyo.co.jp/english/index-e.html

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LC89515 Overview

CD-ROM/CD-I Error Correction/ Host Interface LSI

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Ordering number : EN4272C

CMOS LSI

LC89515K

CD-ROM/CD-I Error Correction/

Host Interface LSI

Overview

The LC89515K is a version of the LC8951 in which

certain aspects of the internal registers have been

improved to make them even easier to use in CD-ROM

and CD-I products. The basic blocks are identical to those

in the LC8951 and these products are software and pin

compatible. Thus this product can replace the LC8951

without change. (However, this product is provided in a

slightly different package: a short lead type QIP-80E as

opposed to the QIP-80A.)

The LC89515K is an error correction and host interface

LSI for use in CD-ROM and CD-I products. This product

integrate in a single chip all CD-ROM specific functions,

including the error correction that was previously

implemented in software on a microprocessor and the CD

player and host computer interfaces that were previously

implemented in discrete components or gate arrays. The

use of the LSI can provide significant improvements in

CD-ROM and CD-I players, including increased transfer

rates, miniaturization, increased reliability, an improved

cost performance ratio, and a more efficient development

period.

Package Dimensions

unit: mm

3174-QFP80E

[LC89515K]

SANYO: QIP80E

Features

• Software and pin compatibility with the LC8951

(Changes were made to internal registers, the SRAM

interface, and other aspects.)

• Support for CD-ROM (mode 1) and CD-I (mode 2,

forms 1 and 2)

• All CD-ROM/CD-I special functions implemented on a

single chip

• Hardware error detection and correction for high speed,

without relying on software

• Real-time error correction: Error correction and

detection are possible without interrupting the host

interface bus.

• Fast transfers: up to 2.3 MB/s (18.4 Mb/s)

• Support for low-speed hosts (multiple block buffering)

• Built-in host interface command FIFO (for easy SCSI

support)

• Built-in 12-byte status FIFO

• CMOS circuits, single 5 V power supply

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

O2095HA (OT)/12395TH (OT)/ 61394TH No. 4272-1/6

LC89515K

Block Functions

The LC89515K consist of three major blocks. This section describes those blocks.

1. CD Player Interface and Data Input Block

This LSI can handle three serial input formats selectable by setting external pin voltages. That is, differences in CD

player serial data formats can be compensated for by setting the CSEL and LMSEL inputs.

Internal operations are synchronized with the input data in block (sector) units using a synchronization detector

circuit. The synchronization circuit not only uses pattern detection on the externally input data, but also performs

synchronization protection with a synchronization signal interpolation circuit. These two synchronization systems

can be turned on or off under program control.

The input data is written to a buffer RAM in 8-bit units after passing through a descrambling circuit. The C2 pointer

(error flag) from the CD player is also written to RAM at this time. Although applications that use the C2 pointer

must provide a 9-bit RAM, the C2 pointer may be omitted and such applications need only provide an 8-bit RAM.

However, note that erasure correction cannot be performed if the C2 pointer is not used.

All input data, including sync, header, subheader and parity (2352 bytes) is stored in RAM in the order received from

the CD player in its entirety.

Furthermore, the LC89515K provides an output pin (MCK) for use with the CD LSI’s oscillator input pin. Therefore,

the number of oscillator elements in the end product can be reduced by selecting the LC89515K master clock

frequency to be twice the CD LSI clock frequency.

2. Error Detection and Correction Block

Error correction code decoding is performed after a full block (sector: 2352 bytes) of data has been stored in RAM.

The LC89515K error correction function operates in real time completely internally. The system software merely

waits for that processing to complete. Furthermore, buffering of data from the CD and transfer to the host computer

are performed simultaneously. That is, the LC89515K can transfer to the host computer data that has been error

corrected without any reduction in the data transfer rate from the CD.

The error correction technique not only consists of error detection and correction, but also supports combination with

erasure correction referencing the C2 pointer. This means that data with high reliability is acquired. The error

detection and correction process can correct single symbol errors, and can correct two symbol errors when combined

with erasure correction.

Furthermore, the error correction algorithm is programmable, and the LC89515K can be instructed to perform a wide

variety of procedures, such as iterative correction or QP/PQ correction, to improve data reliability.

After decoding the error correction codes (ECC), a 32-bit CRC error check is performed using the error detection

codes (EDC). During the CRC check the header and subheader are loaded into LC89515K internal registers.

After completing the CRC check the LC89515K issues a decoding complete interrupt to the control microprocessor.

The microprocessor then reads the header and subheader of the decoded block, the start address of the block in buffer

RAM, and a decoding result status indicator from the LC89515K.

3. Host Interface Block

The data transfer rate to the host computer has been improved significantly, to 2.3 MB/s, and since the amount of

buffering RAM has been increased to 64 kB, up to 27 sectors (blocks) of the CD ROM drive can be stored. This

memory can also be used as a disk cache memory.

The host interface provides an 8-byte FIFO for receiving commands from the host. The host can write up to 8 bytes

of commands at one time by asserting the HWR signal. When the host writes to the FIFO, the LC89515K issues a

command interrupt to the control microprocessor. Here, the commands written to the 8-byte FIFO are never

interpreted by the LC89515K.

When transferring data to the host, the control microprocessor writes the number of bytes to transfer and the start

address in buffer RAM of the block to be transferred. Then, it performs a write operation to the transfer start trigger

low the host reads data items one after another by generating HRD read pulses. If the host reads extremely rapidly,

i.e., over about 2.3 MB/s, then the LC89515K will output a WAIT signal. The host must not set HRD high while

WAIT is low. During this single block transfer operation, the microprocessor does nothing other than waiting for the

transfer complete interrupt that occurs when the transfer is done.

No. 4272-3/6

LC89515 Related Products

	LC89515	LC89515K
Description	CD-ROM/CD-I Error Correction/ Host Interface LSI	CD-ROM/CD-I Error Correction/ Host Interface LSI

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