a
FEATURES
Complete Dual 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output,
±5
mA Drive
Very Low Power: 5 mW
APPLICATIONS
Digitally Controlled Calibration
Portable Equipment
Servo Controls
Process Control Equipment
PC Peripherals
LDA
CS
A/B
DATA
+5 Volt, Parallel Input
Complete Dual 12-Bit DAC
AD8582
FUNCTIONAL BLOCK DIAGRAM
AD8582
DAC A
REGISTER
INPUT A
REGISTER
12
2
INPUT B
REGISTER
12
REFERENCE
V
REF
12
V
DD
12-BIT
DAC A
V
OUTA
LDB
DAC B
REGISTER
12-BIT
DAC B
V
OUTB
AGND
DGND
RST MSB
GENERAL DESCRIPTION
The AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. The reference (V
REF
) is trimmed
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. The user needs only supply a +5
volt supply.
The AD8582 is coded natural binary. The op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving
±
5 mA. Operation down to
4.3 V is possible with output load currents less than 1 mA.
5.0
∆∆VFS
≤
1 LSB
DATA = FFF
H
T
A
= +25
°
C
The high speed parallel data interface connects to the fastest
processors without wait states. The double-buffered input struc-
ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re-
spective DAC registers. An address input decodes DAC A or
DAC B when the chip select
CS
input is strobed. An asynchro-
nous reset input sets the output to zero scale. The MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.
The AD8582 is available in the 24-pin plastic DIP and the sur-
face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V
±
5% power supply
range.
2.0
1.5
V = +5V
DD
T = –55°C, +25°C, +85°C
A
4.8
LINEARITY ERROR – LSB
V
DD
MIN – Volts
1.0
0.5
0.0
–0.5
–1.0
–1.5
4.6
PROPER OPERATION
WHEN V
DD
SUPPLY
VOLTAGE ABOVE
CURVE
4.4
4.2
= +25°C & +85°C
= –55°C
4.0
0.01
0.1
1.0
10
OUTPUT LOAD CURRENT – mA
100
–2.0
0
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
Figure 1. Minimum Supply Voltage vs. Load
Figure 2. Linearity Error vs. Digital Code and Temperature
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
Symbol
DD
= +5.0 V
±
5%, R
L
= No Load, –40°C
≤
T
A
≤
+85°C, unless otherwise noted)
Min
Typ
Max
Units
Condition
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Full-Scale Tempco
MATCHING PERFORMANCE
Linearity Matching Error
REFERENCE OUTPUT
Output Voltage
Output Source Current
Line Rejection
Load Regulation
ANALOG OUTPUT
Output Current
Load Regulation at Half Scale
Capacitive Load
DYNAMIC CHARACTERISTICS
3
Crosstalk
Voltage Output Settling Time
5
Digital Feedthrough
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
TIMING SPECIFICATIONS
3, 6
Chip Select Pulse Width
DAC Select Setup
DAC Select Hold
Data Setup
Data Hold
Load Setup
Load Hold
Load Pulse Width
Reset Pulse Width
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation
7
Power Supply Sensitivity
N
INL
DNL
V
ZSE
V
FS
TCV
FS
∆V
FS
A/B
V
REF
I
REF
LN
REJ
LD
REG
I
OUT
LD
REG
C
L
C
T
t
S
F
T
Note 1
Monotonic
Data = 000
H
Data = FFF
H
,
2
Notes 2 and 3
12
–2
–1
4.079
±
3/4
±
3/4
+0.2
4.095
±
16
±
1
+2
+1
+3
4.111
Bits
LSB
LSB
mV
V
ppm/°C
LSB
2.484
Note 4
I
REF
= 0 mA to 5 mA
Data = 800
H
R
L
= 402
Ω
to
∞,
Data = 800
H
No Oscillation
3
2.500
2.516
–5
0.08
0.1
±
5
3
V
mA
%/V
%/mA
mA
LSB
pF
dB
µs
nV s
1
500
>64
16
35
To
±
1 LSB of Final Value
Signal Measured at DAC Output, While
Changing Data (LDA =
LDB
= “1”)
V
IL
V
IH
I
IL
C
IL
t
CSW
t
AS
t
AH
t
DS
t
DH
t
LS
t
LH
t
LDW
t
RSW
I
DD
P
DISS
PSS
0.8
2.4
Note 3
30
30
0
30
10
20
10
20
30
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5 V
V
IH
= 2.4 V, V
IL
= 0.8 V
V
IL
= 0 V, V
DD
= +5 V
∆V
DD
=
±
5%
4
1
20
5
0.002
7
2
35
10
0.004
10
10
V
V
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
mA
mA
mW
mW
%/%
NOTES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
These parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
REF
pin. Use external buffer if setting up a virtual ground.
5
Settling time is not guaranteed for the first six codes 0 through 5.
6
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7
Power dissipation is a calculated value I
DD
×
5 V.
Specifications subject to change without notice.
–2–
REV. 0
AD8582
ABSOLUTE MAXIMUM RATINGS*
PIN DESCRIPTION
Pin No. Name
Description
V
DD
to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to DGND . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . . . (T
J
max–T
A
)/θ
JA
Thermal Resistance,
θ
JA
24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . . 62°C/W
24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . . 73°C/W
Maximum Junction Temperature (T
J
max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1, 24
V
OUTA
V
OUTB
2
3
4, 21
5
t
CSW
CS
t
AS
A/B
t
AH
6
t
DS
t
DH
D0–D11
t
LS
LDA, LDB
t
LH
t
RSW
t
LDW
7–18
19
20
22
23
RST
t
S
V
OUT
t
S
± 1LSB
ERROR BAND
Timing Diagram
Voltage outputs from the DACs. Fixed
output voltage range of 0 V to 4.095 V
with 1 mV/LSB. An internal
temperature stabilized reference
maintains a fixed full-scale voltage
independent of time, temperature and
power supply variations.
AGND Analog Ground. Ground reference for
the internal bandgap reference voltage,
the DAC, and the output buffer.
DGND Digital ground for input logic.
LDA,
Load DAC register strobes. Transfers
LDB
input register data to the DAC registers.
Active low inputs, Level sensitive latch.
May be connected together to double-
buffer load DAC registers.
MSB
Digital Input: High presets DAC
registers to half scale (800
H
), Low
clears DAC registers to zero (000
H
)
upon
RST
assertion.
RST
Active low digital input that clears the
DAC register to zero, setting the DAC
to minimum scale when MSB pin = 0,
or half-scale when MSB pin = 1.
DB
0–11
Twelve Binary Data Bit Inputs. DB11 is
the MSB and DB0 is the LSB.
CS
Chip Select. Active low input.
A/B
Select DAC A = 0 or DAC B = 1.
V
DD
Positive Supply. Nominal value +5 V,
±
5%.
Nominal 2.5 V reference output
V
REF
voltage. This node must be buffered if
required to drive external loads.
ORDERING INFORMATION*
Model
Temperature
Range
Package
Description
Package
Option
PIN CONFIGURATIONS
N-24
SOL-24
24-Pin Plastic DIP
24-Pin SOIC
1
V
OUTA
AGND
DGND
LDA
MSB
RST
DB0
DB1
DB2
1
2
3
4
5
6
7
8
9
24 V
OUTB
23 V
REF
22 V
DD
21 LDB
20
A/B
24
AD8582AN
–40°C to +85°C 24-Pin Plastic DIP N-24
AD8582AR
–40°C to +85°C 24-Lead SOIC
SOL-24
AD8582Chips +25°C
Die
*For die specifications contact your local Analog Devices sales office. The
AD8582 contains 1270 transistors.
AD8582
TOP VIEW
(Not to Scale)
AD8582
19 CS
TOP VIEW
(Not to Scale) 18 DB11
17 DB10
16 DB9
15 DB8
14 DB7
13 DB6
12
13
DB3 10
DB4 11
DB5 12
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8582 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8582
Table I. Control Logic Truth Table
CS
A/B
LDA
LDB
RST
MSB
Input Register
DAC Register
L
L
L
L
H
H
X
X
H
L
H
L
H
X
X
X
X
X
H
H
L
H
L
^
X
X
X
H
H
H
L
L
^
X
X
X
H
H
H
H
H
H
L
L
^
X
X
X
X
X
X
L
H
X
Write to A
Write to B
Write to A
Write to B
Latched
Latched
Reset to Zero Scale
Reset to Midscale
Latch Reset Value
Latched
Latched
A Transparent
B Transparent
A & B Transparent
Latched
Reset to Zero Scale
Reset to Midscale
Latch Reset Value
^Denotes positive edge triggered.
OPERATION
The AD8582 is a complete, ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. The parallel data interface consists of twelve
data bits, DB0–DB11, an address select pin
A/B,
two load
strobe pins (LDA,
LDB)
and an active low
CS
strobe. In addi-
tion an asynchronous
RST
pin will set all DAC register bits to
zero causing the V
OUT
to become zero volts, or to midscale for
trimming applications when the MSB pin is programmed to
Logic 1. This function is useful for power on reset or system
failure recovery to a known state.
D/A CONVERTER SECTION
BANDGAP
REFERENCE
V
REF
2.5V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
2R
R
BUFFER
2R
R1
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
V
OUT
R2
R
2R
AV = 4.095/2.5
= 1.638V/V
SPDT
N CH FET
SWITCHES
2R
2R
The internal DAC is a 12-bit voltage-mode device with an
output that swings from AGND potential to the 2.5 volt in-
ternal bandgap voltage. It uses a laser trimmed R-2R
ladder which is switched by N channel MOSFETs. The out-
put voltage of the DAC has a constant resistance independent
of digital input code. The DAC output (not available to the
user) is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
Figure 3. Equivalent Schematic of Analog Portion
OUTPUT SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. The rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
The op amp has a 16
µs
typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the Typical Per-
formances section of this data sheet.
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FETs that
will pull an output load directly to GND. The output sourcing
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
V
DD
P-CH
N-CH
V
OUT
AGND
Figure 4. Equivalent Analog Output Circuit
–4–
REV. 0
AD8582
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full-scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
One advantage of the rail-to-rail output amplifiers used in the
AD8582 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current
capability near full scale can be tolerated, operation of the
AD8582 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 1, pro-
vides information for operation below V
DD
= +4.75 V.
TIMING AND CONTROL
The internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. The voltage generated by the reference is
available at the V
REF
pin. Since V
REF
is not intended to drive ex-
ternal loads, it must be buffered. The equivalent emitter fol-
lower output circuit of the V
REF
pin is shown in Figure 3.
Bypassing the V
REF
pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 8
shows broadband noise performance.
POWER SUPPLY
The very low power consumption of the AD8582 is a direct re-
sult of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8582 is
strongly dependent on the actual logic-input voltage levels
present on the DB0–DB11,
CS, A/B,
MSB,
LDA, LDB
and
RST
pins. Since these inputs are standard CMOS logic struc-
tures they contribute static power dissipation dependent on the
actual driving logic V
OH
and V
OL
voltage levels. The graph in
Figure 9 shows the effect on total AD8582 supply current as a
function of the actual value of input logic voltage. Conse-
quently, for optimum dissipation use of CMOS logic versus
TTL provides minimal dissipation in the static state. A V
INL
=
0 V on the DB0–11 pins provides the lowest standby dissipation
of 1 mA typical with a +5 V power supply.
As with any analog system, it is recommended that the AD8582
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
The input registers are level triggered and acquire data from the
data bus during the time period when
CS
is low. The input reg-
ister selected is determined by the
A/B
select pin, see Table I.
for a complete description. When
CS
goes high, the data is
latched into the register and held until
CS
returns low. The
minimum time required for the data to be present on the bus
before
CS
returns high is called the data setup time (t
DS
) as seen
in Timing Diagram. The data hold time (t
DH
) is the amount
of time that the data has to remain on the bus after
CS
goes
high. The high speed timing offered by the AD8582 provides
for direct interface with no wait states in all but the fastest
microprocessors.
The data from the input registers is transferred to the DAC reg-
isters by the active low
LDA
and
LDB
pins. If these inputs are
tied together, a single logic input can perform a double buffer
update of the DAC registers, which in turn simultaneously
changes the analog output voltages to a new value. If the
LDA
and
LDB
pins are wired low, they become transparent. In this
mode the input register data will directly control the output
voltages. Refer to the Control Logic Truth
Table for a com-
plete description.
Unipolar Output Operation
This is the basic mode of operation for the AD8582. The
AD8582 has been designed to drive loads as low as 820Ω in par-
allel with 500 pF. The code table for this operation is shown in
Table II.
Table II. Unipolar Code Table
Hexadecimal
Number in DAC
Register
Decimal Number
in DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+ 4.095
+ 2.049
+ 2.048
+ 2.047
0
REV. 0
–5–
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