Am29BDD160G
Data Sheet
For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration
path for this device. Please refer to the S29CD016G datasheet for specifications and ordering infor-
mation.
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
24960
Revision
D
Amendment
3
Issue Date
February 2, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29BDD160G
16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst
Mode, Dual Boot, Simultaneous Read/Write Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank
while executing erase/program functions in
other bank. (–40°C to 85°C, 56 MHz and below
only)
— Zero latency between read and write opera-
tions
— Two bank architecture: 75%/25%
■
User-Defined x16 or x32 Data Bus
— Burst Mode Read: 90 mA @ 66 MHz max
— Program/Erase: 50 mA max
— Standby mode: CMOS: 60 µA max
■
Minimum 1 million write cycles guaranteed
per sector
■
20 year data retention at 125°C
■
Versatile I/O
TM
control
—
Device generates data output voltages and tol-
erates data input voltages as determined by
the voltage on the V
IO
pin
— 1.65 V to 2.75 V compatible I/O signals
■
Dual Boot Block
— Top and bottom boot in the same device
■
Flexible sector architecture
— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8
Kbytes sectors
■
Manufactured
on
0.17
µm
process
technology
SOFTWARE FEATURES
■
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector
groups to prevent program or erase operations
within that sector (requires only V
CC
levels)
■
Password Sector Protection
— A sophisticated sector protection method to
lock combinations of individual sectors and
sector groups to prevent program or erase op-
erations within that sector using a user-defin-
able 64-bit password
■
Supports Common Flash Interface (CFI)
■
SecSi (Secured Silicon) Sector (256 Bytes)
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
—
Factory locked and identifiable:
16 bytes for
secure, random factory Electronic Serial Num-
ber; remainder may be customer data pro-
grammed by AMD
—
Customer lockable:
Can be read, programmed,
or erased just like other sectors. Once locked,
data cannot be changed
■
Programmable Burst interface
— Interface to any high performance processor
— Modes of Burst Read Operation: Linear Burst:
4 double words (x32), 8 words (x16) and dou-
ble words (x32), and 32 words (x16) with wrap
around
■
Single power supply operation
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
■
Compatible with JEDEC standards (JC42.4)
— Pinout and software compatible with
single-power-supply flash standard
■
Unlock Bypass Program Command
— Reduces overall programming time when issu-
ing multiple program command sequences
■
Data# Polling and toggle bits
— Provides a software method of detecting pro-
gram or erase operation completion
HARDWARE FEATURES
■
Program Suspend/Resume & Erase Sus-
pend/Resume
— Suspends program or erase operations to allow
reading, programming, or erasing in same
bank
■
Hardware Reset (RESET#), Ready/Busy#
(RY/BY#), and Write Protect (WP#) inputs
■
ACC input
— Accelerates programming time for higher
throughput during system production
■
Package options
— 80-pin PQFP
— 80-ball Fortified BGA
PERFORMANCE CHARACTERISTICS
■
High performance read access
— Initial/random access time as fast as 54 ns
— Burst access time as fast as 9 ns for ball grid
array package
■
Ultra low power consumption
Publication#
24960
Rev:
D
Amendment/+3
Issue Date:
February 2, 2005
1
Refer to AMD’s Website (www.amd.com) for the latesst information.
GENERAL DESCRIPTION
T
he Am29BDD160 is a 16 Megabit, 2.5 Volt-only sin-
gle power supply burst mode flash memory device.
The device can be configured for either 1,048,576
words in 16-bit mode or 524,288 double words in
32-bit mode. The device can also be programmed in
standard EPROM programmers. The device offers a
configurable burst interface to 16/32-bit micropro-
cessors and microcontrollers.
To eliminate bus contention, each device has sepa-
rate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls. Additional control in-
puts are required for synchronous burst operations:
Load Burst Address Valid (ADV#), and Clock (CLK).
the two outermost 8 Kbytes sectors of the larger
bank.
The device defaults to the Persistent Sector Protec-
tion mode. The customer must then choose if the
Standard or Password Protection method is most de-
sirable. The WP# Hardware Protection feature is
always available, independent of the other protection
method chosen.
Each device requires only a
single 2.5 or 2.6
Volt power supply
(2.5 V to 2.75 V) for both
read and write functions. A 12.0-volt V
PP
is not
required for program or erase operations, al-
though an acceleration pin is available if faster
programming performance is required.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
The software command set is compatible with the
command sets of the 5 V Am29F and 3 V Am29LV
Flash families. Commands are written to the com-
mand register using standard microprocessor write
timing. Register contents serve as inputs to an inter-
nal state-machine that controls the erase and
programming circuitry. Write cycles also internally
latch addresses and data needed for the program-
ming and erase operations. Reading data out of the
device is similar to reading from other Flash or
EPROM devices.
The
Unlock Bypass
mode facilitates faster pro-
gramming times by requiring only two write cycles to
program data instead of four.
The
Simultaneous Read/Write architecture
pro-
vides simultaneous operation by dividing the
memory space into two banks. The device can begin
programming or erasing in one bank, and then si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for
the completion of program or erase operations. See
Simultaneous Read/Write Operations Overview and
Restrictions on page 13.
The device provides a 256-byte
SecSi™ (Secured
Silicon) Sector
with an one-time-programmable
(OTP) mechanism.
In addition, the device features several levels of sec-
tor protection, which can disable both the program
and erase operations in certain sectors or sector
groups:
Persistent Sector Protection
is a com-
mand sector protection method that replaces the old
12 V controlled protection method;
Password Sec-
tor Protection
is a highly sophisticated protection
method that requires a password before changes to
certain sectors or sector groups are permitted;
WP#
Hardware Protection
prevents program or erase in
The
Versatile I/O™ (V
CCQ
)
feature allows the
output voltage generated on the device to be
determined based on the V
IO
level. This feature
allows this device to operate in the 1.8 V I/O
environment, driving and receiving signals to
and from other 1.8 V devices on the same bus.
In addition, inputs and I/Os that are driven ex-
ternally are capable of handling 3.6 V.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read
array data or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without
affecting the data contents of other sectors. The de-
vice is fully erased when shipped from the factory.
Hardware data protection
measures include
a low V
CC
detector that automatically inhibits
write operations during power transitions. The
password and software sector protection
feature disables both program and erase opera-
tions in any combination of sectors of memory.
This can be achieved in-system at V
CC
level.
The
Program/Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any
period of time to read data from, or program data to,
any sector that is not selected for erasure. True
background erase can thus be achieved.
The
hardware RESET# pin
terminates any opera-
tion in progress and resets the internal state
machine to reading array data.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnel-
ling. The data is programmed using hot electron
injection.
2
Am29BDD160G
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM OF SIMULTANEOUS
OPERATION CIRCUIT . . . . . . . . . . . . . . . . . . . . .
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .
80-Ball Fortified BGA . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
5
6
Table 10. Configuration Register After Device Reset ............ 20
Initial Access Delay Configuration ................................................. 20
SECTOR PROTECTION ..................................................... 20
Sector and Sector Groups ................................................................20
Persistent Sector Protection ........................................................... 20
Password Sector Protection ............................................................ 20
WP# Hardware Protection .............................................................. 20
Special Package Handling Instructions ............................................ 6
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
LOGIC SYMBOLS ...................................................................... 7
X16 Mode ...................................................................................................7
X32 Mode ...................................................................................................7
Persistent Sector Protection ................................................ 21
Persistent Protection Bit (PPB) ........................................................ 21
Persistent Protection Bit Lock (PPB Lock) ................................... 21
Dynamic Protection Bit (DYB) ........................................................ 21
Table 11. Sector Protection Schemes .......................................... 22
Ordering Information ................................................................8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operation ......................................................10
Versatile I/O™ (VIO) Control .................................................11
Word/Double Word Configuration ................................................ 11
Requirements for Reading Array Data ........................................... 11
Persistent Sector Protection Mode Locking Bit ............ 22
Password Protection Mode ................................................. 22
Password and Password Mode Locking Bit .................... 22
64-bit Password ................................................................................... 23
Simultaneous Read/Write Operations Overview
and Restrictions .........................................................................11
Restrictions ............................................................................................. 11
Table 2. Table 2. Bank Assignment for Boot Bank
Sector Devices
................................. 11
Write Protect (WP#) .............................................................23
SecSi™ (Secured Silicon) Sector Protection .....................23
SecSi Sector Protection Bit ...................................................23
Persistent Protection Bit Lock ............................................ 24
Hardware Data Protection .................................................. 24
Low VCC Write Inhibit ..................................................................... 24
Write Pulse “Glitch” Protection .................................................... 24
Logical Inhibit ........................................................................................ 24
Power-Up Write Inhibit .................................................................... 24
VCC and VIO Power-up And Power-down Sequencing ......... 24
Table 12. Sector Addressees for Top Boot Sector
Devices ................................................................................................. 24
Table 13. Sector Addresses for Bottom Boot Sector
Devices ................................................................................................. 26
Simultaneous Read/Write Operations With
Zero Latency ...............................................................................11
Table 3. Top Boot Bank Select
..................... 12
Table 4. Bottom Boot Bank Select
.................. 12
Writing Commands/Command Sequences ......................12
Accelerated Program and Erase Operations ................................ 12
Autoselect Functions ........................................................................... 12
Automatic Sleep Mode (ASM) ..............................................12
Standby Mode ............................................................................12
RESET#: Hardware Reset Pin ...............................................13
Output Disable Mode ..............................................................13
Autoselect Mode ......................................................................13
Table 5. Am29BDD160 Autoselect Codes (High
Voltage Method) ................................................................................. 14
Common Flash Memory Interface (CFI). . . . . . . 28
Table 14. CFI Query Identification String ................................... 28
Table 15. CFI System Interface String ..........................................28
Table 16. CFI Device Geometry Definition ............................... 29
Table 17. CFI Primary Vendor-Specific Extended
Query ................................................................................................... 29
Asynchronous Read Operation (Non-Burst) ................. 14
Figure 1. Asynchronous Read Operation ................................... 14
Synchronous (Burst) Read Operation .................................15
Linear Burst Read Operations ..............................................15
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order ....... 15
CE# Control in Linear Mode ............................................................ 16
ADV# Control In Linear Mode ........................................................ 16
RESET# Control in Linear Mode ..................................................... 16
OE# Control in Linear Mode ........................................................... 16
IND/WAIT# Operation in Linear Mode ....................................... 16
Table 7. Valid Configuration Register Bit Definition for IND/
WAIT# .................................................................................................. 17
Figure 2. End of Burst Indicator (IND/WAIT#) Timing
for Linear 8-Word Burst Operation .......................................... 17
Command Definitions ...............................................................31
Reading Array Data in Non-burst Mode ...........................31
Reading Array Data in Burst Mode .....................................31
Read/Reset Command ...........................................................32
Autoselect Command ............................................................32
Program Command Sequence .............................................32
Accelerated Program Command ........................................32
Unlock Bypass Command Sequence ..................................33
Figure 4. Program Operation ....................................................... 33
Unlock Bypass Entry Command ..........................................33
Unlock Bypass Program Command ...................................33
Unlock Bypass Chip Erase Command ........................................... 34
Unlock Bypass CFI Command ......................................................... 34
Burst Access Timing Control ................................................ 18
Initial Burst Access Delay Control ................................................. 18
Table 8. Burst Initial Access Delay ............................................... 18
Figure 3. Initial Burst Delay Control ........................................... 18
Chip Erase Command ............................................................34
Sector Erase Command .........................................................34
Figure 5. Erase Operation ............................................................. 35
Burst CLK Edge Data Delivery ............................................. 19
Burst Data Hold Control ................................................................... 19
Asserting RESET# During A Burst Access ................................... 19
Sector Erase and Program Suspend Command .............35
Sector Erase and Program Suspend Operation
Mechanics ...................................................................................35
Table 18. Allowed Operations During Erase/Program
Suspend .................................................................................................35
Configuration Register ........................................................... 19
Table 9. Configuration Register Definitions .............................. 19
Sector Erase and Program Resume Command ..............36
Configuration Register Read Command ..........................36
3
Am29BDD160G
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