AT26DF161_14 datasheet, PDF - EEWORLD Datasheet

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AT26DF161_14: DescriptionSerial Peripheral Interface (SPI) Compatible; File Size572KB，34 Pages; ManufacturerAtmel (Microchip)

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AT26DF161_14 Overview

Serial Peripheral Interface (SPI) Compatible

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Features

•

Single 2.7V - 3.6V Supply

•

Serial Peripheral Interface (SPI) Compatible

•

– Supports SPI Modes 0 and 3

66 MHz Maximum Clock Frequency

Flexible, Uniform Erase Architecture

– 4-Kbyte Blocks

– 32-Kbyte Blocks

– 64-Kbyte Blocks

– Full Chip Erase

Individual Sector Protection with Global Protect/Unprotect Feature

– Sixteen 128-Kbyte Physical Sectors

Hardware Controlled Locking of Protected Sectors

Flexible Programming

– Byte/Page Program (1 to 256 Bytes)

Automatic Checking and Reporting of Erase/Program Failures

JEDEC Standard Manufacturer and Device ID Read Methodology

Low Power Dissipation

– 7 mA Active Read Current (Typical)

– 4 µA Deep Power-Down Current (Typical)

Endurance: 100,000 Program/Erase Cycles

Data Retention: 20 Years

Complies with Full Industrial Temperature Range

Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (200-mil wide)

•

16-megabit

2.7-volt Only

Serial Firmware

DataFlash

Memory

AT26DF161

For New

Designs Use

AT25DF161

•

1. Description

The AT26DF161 is a serial interface Flash memory device designed for use in a wide

variety of high-volume consumer based applications in which program code is shad-

owed from Flash memory into embedded or external RAM for execution. The flexible

erase architecture of the AT26DF161, with its erase granularity as small as 4-Kbytes,

makes it ideal for data storage as well, eliminating the need for additional data storage

EEPROM devices.

The physical sectoring and the erase block sizes of the AT26DF161 have been opti-

mized to meet the needs of today's code and data storage applications. By optimizing

the size of the physical sectors and erase blocks, the memory space can be used

much more efficiently. Because certain code modules and data storage segments

must reside by themselves in their own protected sectors, the wasted and unused

memory space that occurs with large sectored and large block erase Flash memory

devices can be greatly reduced. This increased memory space efficiency allows addi-

tional code routines and data storage segments to be added while still maintaining the

same overall device density.

3599H–DFLASH–8/09

The AT26DF161 also offers a sophisticated method for protecting individual sectors against

erroneous or malicious program and erase operations. By providing the ability to individually pro-

tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while

keeping the remaining sectors of the memory array securely protected. This is useful in applica-

tions where program code is patched or updated on a subroutine or module basis, or in

applications where data storage segments need to be modified without running the risk of errant

modifications to the program code segments. In addition to individual sector protection capabili-

ties, the AT26DF161 incorporates Global Protect and Global Unprotect features that allow the

entire memory array to be either protected or unprotected all at once. This reduces overhead

during the manufacturing process since sectors do not have to be unprotected one-by-one prior

to initial programming.

Specifically designed for use in 3-volt systems, the AT26DF161 supports read, program, and

erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for

programming and erasing.

2. Pin Descriptions and Pinouts

Table 2-1.

Symbol

Pin Descriptions

Name and Function

CHIP SELECT:

Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),

and the SO pin will be in a high-impedance state. When the device is deselected, data will not be

accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition

is required to end an operation. When ending an internally self-timed operation such as a program

or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK:

This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

SERIAL INPUT:

The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK.

SERIAL OUTPUT:

The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

WRITE PROTECT:

The WP pin controls the hardware locking feature of the device. Please refer to

“Protection Commands and Features” on page 11

for more details on protection features and the

WP pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will

not be used. However, it is recommended that the WP pin also be externally connected to V

whenever possible.

DEVICE POWER SUPPLY:

The V

pin is used to supply the source voltage to the device.

Operations at invalid V

voltages may produce spurious results and should not be attempted.

GROUND:

The ground reference for the power supply. GND should be connected to the system

ground.

Asserted

State

Type

Low

Input

SCK

Input

Output

Low

Input

GND

Power

AT26DF161

3599H–DFLASH–8/09

AT26DF161

5. Device Operation

The AT26DF161 is controlled by a set of instructions that are sent from a host controller, com-

monly referred to as the SPI Master. The SPI Master communicates with the AT26DF161 via the

SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial

Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode

differing in respect to the SCK polarity and phase and how the polarity and phase control the

flow of data on the SPI bus. The AT26DF161 supports the two most common modes, SPI

Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal

when in the inactive state (when the SPI Master is in standby mode and not transferring any

data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always

output on the falling edge of SCK.

Figure 5-1.

SPI Mode 0 and 3

SCK

MSB

LSB

MSB

LSB

6. Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS

pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.

Following the opcode, instruction dependent information such as address and data bytes would

then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with

the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT26DF161 will be ignored by the device and no operation will be

started. The device will continue to ignore any data presented on the SI pin until the start of the

next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deas-

serted before complete opcode and address information is sent to the device, then no operation

will be performed and the device will simply return to the idle state and wait for the next

operation.

Addressing of the device requires a total of three bytes of information to be sent, representing

address bits A23-A0. Since the upper address limit of the AT26DF161 memory array is

1FFFFFh, address bits A23-A21 are always ignored by the device.

3599H–DFLASH–8/09

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