74FCT377CTQG datasheet, PDF - EEWORLD Datasheet

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74FCT377CTQG: DescriptionQSOP-20, Tube; Categorylogic logic; File Size216KB，7 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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QSOP-20, Tube

74FCT377CTQG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QSOP
package instruction	SSOP, SSOP20,.25
Contacts	20
Manufacturer packaging code	PCG20
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	WITH HOLD MODE
series	FCT
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	8.6868 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
MaximumI(ol)	0.048 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Prop。Delay @ Nom-Sup	5.2 ns
propagation delay (tpd)	5.2 ns
Certification status	Not Qualified
Maximum seat height	1.7272 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	3.937 mm

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IDT74FCT377AT/CT/DT

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

INDUSTRIAL TEMPERATURE RANGE

FAST CMOS OCTAL

D FLIP-FLOP WITH

CLOCK ENABLE

FEATURES:

•

A, C, and D grades

Low input and output leakage

≤

1µA (max.)

CMOS power levels

True TTL input and output compatibility:

– V

= 3.3V (typ.)

– V

= 0.3V (typ.)

High Drive outputs (-15mA I

, 48mA I

)

Meets or exceeds JEDEC standard 18 specifications

Power off disable outputs permit "live insertion"

Available in SOIC and QSOP packages

IDT74FCT377AT/CT/DT

DESCRIPTION:

The IDT74FCT377T is an octal D flip-flop built using an advanced dual

metal CMOS technology. The IDT74FCT377T has eight edge-triggered,

D-type flip-flops with individual D inputs and O outputs. The common

buffered Clock (CP) input loads all flip-flops simultaneously when the Clock

Enable (CE) is low. The register is fully edge-triggered. The state of each

D input, one set-up time before the low-to-high clock transition, is transferred

to the corresponding flip-flop’s O output. The

input must be stable only

one set-up time prior to the low-to-high transition for predictable operation.

•

FUNCTIONAL BLOCK DIAGRAM

D Q

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 2009

DSC-2630/14

74FCT377CTQG Related Products

	74FCT377CTQG	74FCT377CTSOG	74FCT377CTSOG8	74FCT377ATSOG8	74FCT377CTQG8	74FCT377ATSOG
Description	QSOP-20, Tube	SOIC-20, Tube	SOIC-20, Reel	SOIC-20, Reel	QSOP-20, Reel	SOIC-20, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Parts packaging code	QSOP	SOIC	SOIC	SOIC	QSOP	SOIC
package instruction	SSOP, SSOP20,.25	SOP, SOP20,.4	SOP, SOP20,.4	SOP, SOP20,.4	SSOP, SSOP20,.25	SOP, SOP20,.4
Contacts	20	20	20	20	20	20
Manufacturer packaging code	PCG20	PSG20	PSG20	PSG20	PCG20	PSG20
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Other features	WITH HOLD MODE	WITH HOLD MODE	WITH HOLD MODE	WITH HOLD MODE	WITH HOLD MODE	WITH HOLD MODE
series	FCT	FCT	FCT	FCT	FCT	FCT
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e3	e3	e3	e3	e3	e3
length	8.6868 mm	12.8 mm	12.8 mm	12.8 mm	8.6868 mm	12.8 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
MaximumI(ol)	0.048 A	0.048 A	0.048 A	0.048 A	0.048 A	0.048 A
Humidity sensitivity level	1	1	1	1	1	1
Number of digits	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of terminals	20	20	20	20	20	20
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SOP	SOP	SOP	SSOP	SOP
Encapsulate equivalent code	SSOP20,.25	SOP20,.4	SOP20,.4	SOP20,.4	SSOP20,.25	SOP20,.4
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Prop。Delay @ Nom-Sup	5.2 ns	5.2 ns	5.2 ns	7.2 ns	5.2 ns	7.2 ns
propagation delay (tpd)	5.2 ns	5.2 ns	5.2 ns	7.2 ns	5.2 ns	7.2 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.7272 mm	2.6416 mm	2.65 mm	2.65 mm	1.7272 mm	2.6416 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.635 mm	1.27 mm	1.27 mm	1.27 mm	0.635 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	30	30	30	NOT SPECIFIED	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	3.937 mm	7.5 mm	7.5 mm	7.5 mm	3.937 mm	7.5 mm
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-	IDT (Integrated Device Technology)
Base Number Matches	-	1	1	1	1	-

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