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SDC-14560
SYNCHRO-TO-DIGITAL CONVERTER
FEATURES
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•
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DESCRIPTION
The SDC-14560 is a series of high-reliability Synchro or Resolver-to-
Digital (S/R-D) converters with user-programmable resolution of 10,
12, 14, or 16 bits. Other features of the SDC-14560 are high-quality
velocity output and hermetic seal.
User-programmable resolution has been designed into the SDC-
14560 to increase the capabilities of modern motion control systems.
The precise positioning attained at 16-bit resolution and fast tracking
of a 10-bit device are now available from one 36- pin double DIP
hybrid. Velocity output (VEL) from the SDC-14560 is a ground-based
voltage of 0 to ±10 VDC with a linearity to 0.7%. Output voltage is
positive for an increasing angle.
The SDC-14560 series accepts broadband inputs: 360 Hz to 1 kHz, or
47 Hz to 1 kHz. The digital angle output from the SDC-14560 is a
natural binary code, parallel positive logic and is TTL/CMOS compat-
ible. Synchronization to a computer is accomplished via a converter
busy (CB) and an inhibit (
INH
) input.
Programmable Resolution:
10, 12, 14 or 16 Bits
High-Quality Velocity Output
Eliminates Tachometer
Accuracy to ±1.3 Arc Minutes
Small Size
Synchro or Resolver Input
Synthesized Reference
Eliminates 180° Lock-Up
Control Transformer Mode
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APPLICATIONS
Because of its high reliability, accuracy, small size, and low power consump-
tion,
the SDC-14560 is ideal for the most stringent and severe indus-
trial and military ground or avionics applications. All models are avail-
able with MIL-PRF-38534 processing as a standard option.
Designed with three-state output, the SDC-14560 is especially well
suited for use with computer-based systems. Among the many possi-
ble applications are radar and navigation systems, fire control sys-
tems, flight instrumentation, and flight trainers or simulators.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7771
All trademarks are the property of their respective owners.
©
®
1987, 1999 Data Device Corporation
Inductosyn is a registered trademark of Farrand Controls Corporation
SOLID STATE SYNCHRO INPUT OPTION
SIN
COS
COS
VOLTAGE
FOLLOWER
BUFFER
SIN
SIN
SOLID STATE RESOLVER INPUT OPTION
SOLID STATE RESOLVER INPUT OPTION
S1
RESOLVER
CONDITIONER
SIN
S2
V
REF IN
RH
RL
+15 V
-15 V
Data Device Corporation
www.ddc-web.com
S1
S2
S3
S4
INPUT OPTIONS
COS
INTERNAL
DC
REFERENCE
BIT
REFERENCE
CONDITIONER
R
SYNTHESIZED
REF
BIT DETECT
DIFF
GAIN OF
2, 7
e
DEMOD
SIN
( - )
D
VEL
ERROR
PROCESSOR
T
VCO
U
E
VEL
DIFF
GAIN
OF 2
e
GAIN
1 LSB ANTIJITTER FEEDBACK
CB
U
50 ns DELAY
T
0.4-1 µs
Q
INH
3 STATE
TTL BUFFER
EDGE
T
TRIGGERED
LATCH
+10 V
INTERNAL DC
REF V (+5 V)
A
B
RESOLUTION CONTROL
S
16-BIT U-D
COUNTER
INHIBIT
TRANSPARENT
LATCH
INH
POWER
SUPPLY
CONDITIONER
+15
BITS 9-16
EL
ELECTRONIC
SCOTT T
S3
COS
2
SIN
INPUT OPTION
COS
HIGH ACCURACY
CONTROL
TRANSFORMER
16-BIT CT
TRANSPARENT
LATCH
+5 V
DIGITAL
ANGLE
3 STATE
TTL BUFFER
16-BIT OUTPUT
TRANSPARENT
LATCH
EM
BITS 1-8
SDC-14560
T-12/09-0
FIGURE 1. SDC-14560 BLOCK DIAGRAM
Apply over temperature range power supply range reference fre-
quency and amplitude ranges; 10% signal amplitude variation;
and up to 10% harmonic distortion in the reference.
PARAMETER
RESOLUTION
(1)
ACCURACY
(2)
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Ranges
Nominal 400 Hz Units
Nominal 60 Hz Units
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance balanced)
Synchro
Zin Line to Line
Zin Each Line to Gnd
Resolver
Zin Single Ended
Zin Differential
Zin Each Line to Gnd
Common Mode Range
Direct (1.0 VL-L)
Input Signal Type
sin/cos Voltage Range
Max Voltage w/o Damage
Input Impedance
REFERENCE SYNTHESIZER
±Sig/Ref Phase Shift
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
UNIT
Bits
Min
LSB
LSB
VALUE
10, 12, 14, or 16
±4, ±2, or ±1 +1LSB
1 max
1 max in the 16th bit
TABLE 1. SDC-14560 SPECIFICATIONS
TABLE 1. SDC-14560 SPECIFICATIONS (CONT.)
PARAMETER
Output Parallel Data
Converter Busy (CB)
BIT
Drive Capability
UNIT
bits
VALUE
10, 12, 14, or 16 parallel
lines; natural binary angle,
positive logic
0.4 to 1 µs positive pulse;
leading edge initiates
counter update.
Logic 0 for fault.
50 pF plus rated logic drive.
Logic 0; 1 TTL load,
1.6 mA at 0.4 Vmax
Logic 1; 10 TTL loads
0.4 mA at 2.8 V min
High Z; 10 µA//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply minus
100 mV min driving CMOS
See TABLES 3 and 4
50 per LSB of error
(10-bit mode)
25 per LSB of error
(12-bit mode)
12.5 per LSB of error
(14-bit mode)
6.3 per LSB of error
(16-bit mode)
3 min
See TABLE 3.
Hz
Hz
Vrms
Ohm
Ohm
V
360-1000
47-1000
4-130
250k min
500k min
210 peak max
500 transient peak
ANALOG OUTPUTS (3)
Velocity (VEL)
AC error (e)
mV rms
Ohm
Ohm
Ohm
Ohm
Ohm
V
11.8 VL-L
17.5k
11.5k
11.8 VL-L
23k
46k
23k
25 max
90 VL-L
130k
85k
26 VL-L
50k
100k
50k
60 max
Load
DYNAMIC
CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS (Note 3)
Nominal Voltage
Voltage Range
Max Voltage w/o Damage
Current
TEMPERATURE RANGES
Operating
-30X
-10X
Storage
THERMAL RESISTANCE
Junction to Case,
θ
jc
Junction to Ambient,
θ
ja
PHYSICAL
CHARACTERISTICS
Size
Weight
TRANSFORMERS
CHARACTERISTICS
(See ordering information for
list of Transformers. Reference
Transformers are Optional for
Both Solid-State and Voltage
Follower Input Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
kOhm
Vrms
Ohm
sin and cos resolver signals
referenced to converter inter-
nal DC reference V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M//10 pF
voltage follower
60 max, 45 typ
±%
V
mA max
+15 V
5
+18
25
+5 V
10
+8
10
-15 V
5
-18
15
Deg
°C
°C
°C
°C/W
°C/W
0 to +70
-55 to +125
-65 to +150
8
20
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
S (Control Transformer)
Resolution Control (A & B)
(Unused Output Data
Bits Are Set to 0)
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 µA max P.U.
current source
to +5 V//5 pF max
CMOS transient protected
Logic 0 inhibits
Data stable after 0.5 µs
Logic 0 enables
Logic 1 High Z
Logic 0 enables
Logic 1 High Z
Logic 0 for use as CT
B
0
0
1
1
A
0
1
0
1
Resolution
10 bits
12 bits
14 bits
16 bits
in. (mm) 1.9 x 0.78 x 0.21
(48.3 x 19.8 x 5.3)
36-Pin Double Dip
oz. (g) 0.7 max (20)
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
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3
SDC-14560
T-12/09-0
TABLE 1. SDC-14560 SPECIFICATIONS (CONTD)
PARAMETER
TRANSFORMERS
CHARACTERISTICS (contd)
Signal Transformer
Carrier Frequency Range
Breakdown Voltage to GND
Minimum Input Impedances
(Balanced)
90 V L-L
26 V L-L
11.8 V L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common-Mode
Voltage
Output Description
UNIT
VALUE
360- 1000 Hz
700 V peak
Synchro Z
IN
(Z
SO
) Resolver Z
lN
180
Ω
-
20k
Ω
100k
Ω
30k
Ω
30k
Ω
sin(θ + 120°)cosωt, and sin(θ + 240°)cosωt are internally con-
verted to resolver format; sinθcosωt and cosθcosωt. Direct inputs
accept
1 Vrms inputs in resolver form, (sinθcosωt and
cosθcosωt) and are buffered prior to conversion. FIGURE 2 illus-
trates synchro and resolver signals as a function of the angle
θ.
The solid state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection.
Input
impedance is maintained with power off.
+V
S1-S3 = V
MAX
MAX
SIN
Output Voltage
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode
Voltage
Output Description
Output Voltage
47 - 440 Hz
10 - 100 V rms L-L; 90 V rms
L- L nominal
148 kΩ min L-L balanced
resistive
±500 V rms transformer isolated
Resolver output,
- sine (- S) + cosine (+C)
derived from op-amps.
Short circuit proof.
1.0 V rms nominal riding on
ground reference V.
Output voltage level tracks
input level.
4 mA typ, 7 mA max from
+15 V supply.
In Phase with
RH-RL of Converter
and R2-R4 of RX.
47 - 440 Hz
80 - 138 V rms; 115 V rms
nominal resistive
600 kΩ min resistive
500 V rms transformer isolated
+R (in phase with RH-RL)
and - R (in phase with RL- RH)
derived from op-amps. Short
Circuit proof.
3.0 V nominal riding on ground
reference V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from
+15 V supply.
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
CCW
(DEGREES)
-V
MAX
S3-S2 = V
S2-S1 = V
SIN(
MAX
SIN(
MAX
Standard Synchro Control
Outputs as
Standard Synchro Control
Zero (EZ). Transmitter (CX)
Outputs
a Function ofCCW Rotation
as a Function of CCW Rotation
from Electrical
Transmitter (CX)
From Electrical Zero (EZ).
+V
MAX
S2-S4 = V
MAX
COS
0
360
30
90
150
210
270
330
CCW
(DEGREES)
-V
MAX
S1-S3 = –V
MAX
SIN(
Standard Resolver Control Transmitter (RX) Outputs as Function of CCW
Standard Resolver Control
Electrical Zero (EZ) with
Outputs as a
a
Function of CCW Rotation
Transmitter (RX)
R2-R4 Excited.
Rotation From
From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
SOLID-STATE BUFFER INPUT PROTECTION -
TRANSIENT VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The current AC peak
+DC common mode voltage should not exceed the values in
TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 500 V specification. These transients can destroy the
thin-film input resistor network in the hybrid. Therefore, 90 V
l
-
l
solid-state input modules may be protected by installing voltage
suppressors as shown. Voltage transients are likely to occur
whenever synchro or resolver are switched on and off. For
instance, a 1000 V transient can be generated when the primary
of a CX or TX driving a synchro or resolver input is opened. See
FIGURE 3.
Power Required
Note:
(1) Pin programmable.
(2) See TABLE 6.
(3) It is recommended to place 0.1uF external bypass capacitors on the
±15V supplies for higer noise immunity on the analog Velocity and
AC error (e) outputs.
INTRODUCTION
The circuit shown in FIGURE 1, the SDC-14560 Block Diagram,
consists of three main parts: the signal input; a feedback loop,
whose elements are the control transformer, demodulator, error
processor, VCO and up-down counter; and digital interface cir-
cuitry including various latches and buffers.
SIGNAL INPUTS
The SDC-14560 series offers three input options: synchro,
resolver, and direct. In a synchro or resolver, shaft angle data is
transmitted as the ratio of carrier amplitudes across the input
terminals. Synchro signals, which are of the form sinθcosωt,
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FEEDBACK LOOP
The feedback loop produces a digital angle
φ
which tracks the
analog input angle
θ
to within the specified accuracy of the con-
SDC-14560
T-12/09-0
FOR 90 V SYNCHRO INPUTS
S3
CR1
S1
CR2
S2
RL
S1
CR1,
CR3 are 1N6136A, bipolar transient voltage suppressors
CR1, CR2, and
CR2, and CR3 are 1N6136A, bipolar transient voltage suppressors
or equivalent.
or equivalent.
FOR 90 V RESOLVER INPUTS
S1
S2
90 V L-L
RESOLVER
INPUT
S3
S4
CR4
CR5
S3
S4
CR4 and CR5 are 1N6136A, bipolar transient voltage
S1
S2
HYBRID
S3
RH
CR3
S2
HYBRID
1N6071A
phase with the signal input, and quadrature errors will therefore
be eliminated. The synthesized reference circuit also eliminates
the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Error = Quad/F.S. signal * tan(α)
Where: Error is in radians
Quad/F.S. signal is per unit quadrature input level.
α
= signal to reference phase shift in degrees.
A typical example of the magnitude of this source of error is as
follows:
Quad/F.S. signal = .001
α
=6
Error = 0.35 min
≈1
LSB in the 16th bit.
Note: Quad/F.S. is composed of static quadrature which is
specified by the resolver or synchro supplier plus the speed volt-
age which is given by:
Speed Voltage = rotational speed/carrier frequency
Where: Speed Voltage is the per unit ratio of electrical rotational
speed in RPS divided by carrier frequency in Hz.
This error is totally negligible for up to 14-bit converters. For
16-bit converters, where the highest accuracy possible is needed
and where the quadrature and phase shift specifications can be
higher, this source of error could be significant. The reference
synthesizer circuit in the converter which derives the reference
from the input signal essentially sets
α
to zero resulting in com-
plete rejection of the quadrature.
CR4 and CR5 are 1N6136A, bipolar
or equivalent.
voltage suppressors or equivalent.
suppressors
transient
FIGURE 3. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
verter. The control transformer performs the following trigono-
metric computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
where
θ
is the angle representing the resolver shaft position, and
φ
is the digital angle contained in the up/down counter. The track-
ing process consists of continually adjusting
φ
to make (θ -
φ)
0, so that
φ
will represent the shaft position
θ.
The output of the
demodulator is an analog DC level proportional to sin(θ -
φ).
The
error processor receives its input from the demodulator and inte-
grates this sin(θ -
φ)
error signal which then drives a Voltage-
Controlled Oscillator (VCO). The VCO’s clock pulses are accu-
mulated by the up/down counter. The velocity voltage accuracy,
linearity and offset are determined by the quality of the VCO.
Functionally, the up/down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a Type II tracking servo. In a Type II servo, the VCO
always settles to a counting rate which makes dφ/dt equal to dθ/
dt without a lag. The output data will always be fresh and avail-
able as long as the maximum tracking rate of the converter is not
exceeded.
DIGITAL INTERFACE
The digital interface circuitry has three main functions: to latch
the output bits during an inhibit command so that the stable data
can be read; to furnish both parallel and three-state data formats;
and to act as a buffer between the internal CMOS logic and the
external TTL logic.
In the SDC-14560, applying an inhibit command will lock the
data in the transparent latch without interfering with the continu-
ous tracking of the feedback loop. Therefore, the digital angle is
always updated, and the inhibit can be applied for an arbitrary
amount of time. The inhibit transparent latch and the 50 ns delay
are part of the inhibit circuitry. The inhibit circuitry is described in
detail in the logic input/output section.
SYNTHESIZED REFERENCE
The synthesized reference section of the SDC-14560 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals lead the reference signal
(RH and RL) by about 6°. When an uncompensated reference
signal is used to demodulate the control transformer’s output,
quadrature voltages are not completely eliminated. In a 12- or
14-bit converter it is not necessary to compensate for the refer-
ence signal’s phase shift. A 6° phase shift will, however, cause
problems for the one minute accuracy converters. As shown in
FIGURE 1, the converter synthesizes its own cos(ωt +
α)
refer-
ence signal from the sinθcos(ωt +
α),
cosθcos(ωt +
α)
signal
inputs and from the cos
ωt
reference input. The phase angle of
the synthesized reference is determined by the signal input The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
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LOGIC INPUT/OUTPUT
Logic angle outputs consist of 10, 12, 14 or 16 parallel data bits
and CONVERTER BUSY (CB). All logic outputs are short-circuit
proof to ground and +5 Volts. The CB output is a positive, 0.4 to
1.0 µs pulse. Data changes about 50 ns after the leading edge
of the pulse because of an internal delay. Data is valid 0.2 µs
after the leading edge of CB, the angle is determined by the sum
of the bits at logic “1”. Digital outputs are three-state and two
bytes wide; bits 1-8 (MSBs) are enabled by the signal EM, bits
9-16 (LSBs) are enabled by the signal EL. Outputs are valid
SDC-14560
T-12/09-0
FPGA/CPLD
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