SP5748/KG/QP1S datasheet, PDF - EEWORLD Datasheet

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SP5748/KG/QP1S: DescriptionPLL/Frequency Synthesis Circuit, BIPolar, PDSO16; CategoryAnalog mixed-signal IC The signal circuit; File Size126KB，9 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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SP5748/KG/QP1S Overview

PLL/Frequency Synthesis Circuit, BIPolar, PDSO16

SP5748/KG/QP1S Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	113278666
Parts packaging code	SSOP
Contacts	16
Reach Compliance Code	unknown
YTEOL	0
JESD-30 code	R-PDSO-G16
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Certification status	Not Qualified
Maximum supply current (Isup)	20 mA
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	BIPOLAR
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL

SP5748/KG/QP1S Preview

SP5748

2·4GHz Very Low Phase Noise PLL

DS4875 Issue 2.0 October 1999

Features

Complete 2.4 GHz Single Chip System

Ordering Information

SP5748/KG/MP1S (Tubes)

SP5748/KG/MP1T (Tape and Reel)

SP5748/KG/QP1S (Tubes)

SP5748/KG/QP1T (Tape and Reel)

and allows for coarse tuning in the up-converter application

and fine tuning in the down-converter.

Comparison frequencies are obtained either from a crystal

controlled on-chip oscillator or from an external source.

A buffered reference frequency output is also available to drive

a second SP5748. The device also contains 2 switching ports.

(for faster device refer to SP5768)

Optimised for Low Phase Noise, with Comparison

Frequencies up to 4 MHz

No RF Prescaler

Selectable Reference Division Ratio

Reference Frequency Output

Selectable Charge Pump Current

Integrated Loop Amplifier

Two Switching Ports

Low Power Replacement for SP5658 and SP5668

Power Consumption 72mW with V

= 5·5V and all Ports

off

Downwards Software Compatible with SP5658

ESD Protection 2kV min., MIL-STD-883B Method 3015

Cat.1 (Normal ESD handling procedures should be

observed)

Absolute Maximum Ratings

Supply voltage, V

RF differential input voltage

RF input DC offset

Port voltage

Charge pump DC offset

Varactor drive DC offset

Crystal DC offset

Buffered reference output

Data, clock and enable DC offset

Storage temperature

Junction temperature

MP14 thermal resistance

Chip to ambient,

Chip to case,

20·3V

17V

2·5V

20·3

to V

10·3V

20·3

to V

10·3V

20·3

to V

10·3V

20·3

to V

10·3V

20·3

to V

10·3V

20·3

to V

10·3V

20·3

to V

10·3V

255°C

1125°C

1150°C

81°C/W

27°C/W

Applications

TV, VCR and Cable Tuning Systems

Communications Systems

The SP5748 is a single chip frequency synthesiser designed

for tuning systems up to 2.4 GHz and is optimized for low

phase noise with comparison frequencies up to 4 MHz. It is

designed to be downwards software compatible with the

SP5658. The RF programmable divider contains a front end

dual-modulus

416/17

functioning over the full operating range

CRYSTAL

CAP

INPUT

13-BIT

COUNT

REFERENCE

DIVIDER

16/17

4-BIT

COUNT

CHARGE

PUMP

CRYSTAL

PUMP

DRIVE

17-BIT LATCH

DATA

CLOCK

ENABLE

6-BIT LATCH

REF

DATA

INTERFACE

3-BIT

LATCH AND

PORT/TEST MODE

INTERFACE

PORT P1/OC

PORT P0/OP

Figure 1 SP5748 block diagram (MP14 pinout)

SP5748

CHARGE PUMP

CRYSTAL CAP

CRYSTAL

ENABLE

DATA

CLOCK

PORT P1/OC

DRIVE

RF INPUT

REF

DRIVE

RF INPUT

RFINPUT

REF

PORTP0/OP

CRYSTAL CAP

CRYSTAL

ENABLE

DATA

CLOCK

PORT P1/OC

PORT P0/OP

5748

MP14

Figure 2 Pin connections - top view

QP16

Electrical Characteristics

Test conditions (unless otherwise stated): Tamb =

240°C

180°C,

= 4·5V to 5·5V. These characteristics are

guaranteed by either production test or design. They apply within the specified ambient temperature and supply

voltage ranges unless otherwise stated.

Value

Characteristic

Supply current

RF input

Frequency range

Input voltage

Input impedance

Data, clock and enable

Input high voltage

Input low voltage

Input current

Hysteresis

Clock rate

Bus timing

Data set up

Data hold

Enable set up

Enable hold

Clock to enable

Charge pump

Output current

Output leakage

Drive output current

Crystal frequency

External reference

Input frequency

Drive level

Buffered reference output

Output amplitude

Output impedance

11,12

5,6,4

210

0·8

5,6,4

300

600

300

600

300

2,3

500

0·7

µA

Vp-p

kHz

µA

MHz

Vp-p

Ω

PIN1

= 2V, See Table 1

PIN1

= 2V, V

15·0V,

AMB

= 25°C

PIN14

= 0·7V

See Figure 5 for application

Sinewave coupled via 10nF blocking capacitor

AC coupled, see Note 1

2-20MHz

cont…

Min.

Typ.

Max.

Units

Conditions

2400 MHz

300 mVrms 150MHz to 2400MHz

300 mVrms 80MHz to 150MHz

See Figure 3

All input conditions

0·5

0·2

610

0·5

0·35

250

SP5748

Electrical Characteristics

(continued)

Value

Characteristic

Comparison frequency

Equivalent phase noise at

phase detector

RF division ratio

Reference division ratio

Output Ports P0 and P1

Sink current

Leakage current

Min.

2148

240

7,8

µA

131071

320

Typ.

Max.

Units

Conditions

MHz

dBc/Hz At 10kHz SSB with 2MHz comparison

from 4MHz crystal

See Table 2

See Note 2

PORT

= 0·7V

PORT

= V

NOTES

1. Reference output disabled by connecting to V

if required.

2. Output ports high impedance on power-up, with data, clock and enable at logic ‘0’.

Functional description

The SP5748 contains all the elements necessary, with the

exception of a frequency reference, loop filter and external

high voltage transistor, to control a varicap tuned local

oscillator, so forming a complete PLL frequency

synthesised source. The device allows for operation with

a high comparison frequency and is fabricated in high

speed logic, which enables the generation of a loop with

excellent phase noise performance, even with high

comparison frequencies.

The block diagram is shown in Figure 1 and packages

and pin allocations in Figure 2.

The SP5748 is controlled by a standard 3-wire bus

comprising data, clock and enable inputs. The

programming word contains 26 bits, two of which are used

for port selection, 17 to set the programmable divider ratio,

4 bits to select the reference division ratio (bits RD and

R0-R2, see Table 2), two bits to set charge pump current,

bits C0 and C1 (see Table 1) and the remaining bit to access

test modes (bit T0, see Table 3)). The programming data

format is shown in Figure 4.

The clock input is disabled by an enable low signal, data is

therefore only loaded into the internal shift registers during

an enable high and is clocked into the controlling buffers

by an enable high to low transition. This load is also

synchronised with the programmable divider so giving

smooth fine tuning.

The RF signal is fed to an internal preamplifier, which

provides gain and reverse isolation from the divider signals.

The output of the preamplifier is fed to the 17-bit fully

programmable counter, which is of MN+A architecture. The

M counter is 13 bits and the A counter 4 bits.

The output of the programmable divider is fed to the phase

comparator where it is compared in both phase and

frequency domain with the comparison frequency. This

frequency is derived either from the on-chip crystal

controlled oscillator or from an external reference source.

In both cases the reference frequency is divided down to

the comparison frequency by the reference divider which

is programmable into1 of 16 ratios as described in Table 2.

The output of the phase detector feeds the charge pump

and loop amplifier section, which when used with an

external high voltage transistor and loop fiIter integrates

the current pulses into the varactor line voltage. The charge

pump current setting is described in Table 1.

A buffered crystal reference frequency suitable for driving

further synthesisers is available from pin 9. If not required

this output can be disabled by connecting to V

The programmable divider output divided by 2, f

/2 and

comparison frequency, f

COMP

, can be switched to ports P0

and P1 respectively by switching the device into test mode.

The test modes are described in Table 3.

SP5748

j0.5

j0.2

0.2

0.5

0·5GHz

1GHz

2j5

2j0.2

2·4GHz

S11: Z

= 50Ω

Normalised to 50Ω

2j0.5

2j1

2j2

Figure 3 RF input impedance

CLOCK

ENABLE

DATA

MSB

FREQUENCY

DATA

LSB

to 2

R2, R1, R0

P1, P0

C1, C0

Programmable divider ratio control bits

Reference divider control bits (see Table 2)

Reference divider mode select (see Table 2)

Port control bits (see Table 3)

Charge pump current bits (see Table 1)

Test mode enable bit

Figure 4 Data format

Charge pump current (

6230

61000

6115

6500

68p

150p











SP5748

Table 1 Charge pump current

Figure 5 Crystal oscillator application

SP5748

Division ratio

128

256

160

320

Test mode description

Normal operation

Charge pump sink

Charge pump source

Charge pump disable

Port P1= f

COMP

, P0 = f

Table 3 Test modes

300

VIN (mVRMS INTO 50Ω)

OPERATING WINDOW

Table 2 Reference divider control

80 150

1000

2400

FREQUENCY (MHz)

Figure 6 Typical input sensitivity

1·6GHz

50-900MHz

1650-2400MHz

SP5748

10n

VCO

38·9MHz

SP5748

Figure 7 Example of double conversion from VHF/UHF frequencies to TV IF

130V

68p

15n

13·3k

Optional application using

on-chip crystal controlled

oscillator

18p

68p

22k

16k

BCW31

47k

2·2n

112V

TUNER

15V

OSCILLATOR

OUTPUT

REFERENCE

ENABLE

CONTROL

MICRO

DATA

CLOCK

5748

Figure 8 Typical application of SP5748

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SP5748/KG/QP1S Related Products

	SP5748/KG/QP1S	SP5748/KG/QP1T
Description	PLL/Frequency Synthesis Circuit, BIPolar, PDSO16	PLL Frequency Synthesizer, BIPolar, PDSO16, QP-16
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	SSOP	SSOP
Contacts	16	16
Reach Compliance Code	unknown	unknown
JESD-30 code	R-PDSO-G16	R-PDSO-G16
Number of terminals	16	16
Maximum operating temperature	85 °C	80 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP
Encapsulate equivalent code	SSOP16,.25	SSOP16,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified
Maximum supply current (Isup)	20 mA	20 mA
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	YES
technology	BIPOLAR	BIPOLAR
Temperature level	INDUSTRIAL	OTHER
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL

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