TQ8224 datasheet, PDF - EEWORLD Datasheet

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TQ8224: DescriptionMux/Demux, PBGA208, 23 X 23 MM, BGA-208; CategoryWireless rf/communication Telecom circuit; File Size198KB，20 Pages; ManufacturerQorvo; Websitehttps://www.qorvo.com

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TQ8224 Overview

Mux/Demux, PBGA208, 23 X 23 MM, BGA-208

TQ8224 Parametric

Parameter Name	Attribute value
Maker	Qorvo
Parts packaging code	BGA
package instruction	LBGA,
Contacts	208
Reach Compliance Code	unknown
JESD-30 code	S-PBGA-B208
length	23 mm
Number of terminals	208
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Certification status	Not Qualified
Maximum seat height	1.65 mm
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH MUX/DEMUX
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	23 mm

TQ8224 Preview

S E M I C O N D U C T O R, I N C .

The TQ8224 operates in one of two different time-division demultiplexing

modes, making it extremely flexible for telecom, ATM and networking

applications. The serial 2.48832 Gb/s data stream can be demultiplexed

into either an 8-bit wide 311.04 MHz data bus or a 16-bit wide 155.52 MHz

data bus. Internal data inversion is also available. The device generates

byte-wise parity check bits for the demultiplexed data and provides

associated clock outputs for the different modes. Parity checking is not

required for normal device operation.

Features

• Single-chip, 1:8 or 1:16

Demultiplexer with integrated

clock and data recovery

• Differential Analog Data Input

• SONET/SDH compliant for

2.48832 Gb/s jitter tolerance &

transfer

• Internal PLL with NRZ phase

detector ensures sampling of

incoming data stream occurs in

center of data eye

• Static phase adjustment on

recovered clock position

• High speed input data bit slipper

for use in framing

• External RC-based loop filter

• Four output clock rates at

311.04, 155.52, 77.76, and 38.88

MHz.

• Internal byte-wise even/odd

parity bit generator (mode

programable)

• Direct-coupled differential PECL

low-speed outputs

• 23mm 208-pin BGA package

• 5V single supply

• –40 to +125

C case operating

temperature.

The TQ8224 provides added flexibility through a selectable internal/external

Voltage Controlled Oscillator(VCO) as well as a selectable internal Phase

Locked Loop (PLL). If an external high frequency clock is utilized a single-

ended or differential AC coupled clock may be used.

The internal PLL contains a NRZ phase detector which enables it to adjust

the phase of the internal clock such that sampling of the incoming data

stream occurs in the middle of the the data eye. An offset control allows

adjustment

±128

pS around this nominal position.

Operating from a single +5V supply, the TQ8224 provides fully compliant

functionality and performance, utilizing direct-connected differential PECL

(DPECL) levels for the 8 and 16 bit busses. The TQ8224 can also provide

direct connection to high-speed output lines using ECL levels, if supplies

are connected to -5.2V. However, with ECL operation, the TTL control

signal grounds are referenced to -5.2V.

The TQ8224 is fully compliant with SONET/SDH jitter tolerance and

transfer specifications. A TTL level LOCK signal is supplied to indicate

when the frequency difference between the internal 38.88 MHz clock and

the external 38.88 MHz clock is less than 488 ppm.

TELECOM

PRODUCTS

The TQ8224 is a multi-configuration SONET/SDH OC48/STM16 CDR/

DEMUX that regenerates and re-times serial 2.48832 Gb/s data. It

recovers the 2.48832 GHz clock from the data stream and frequency

divides it to generate control signals and clocks used to perform the

demultiplexing function.

TQ8224

PRELIMINARY DATA SHEET

OC48/STM16

DEMUX/CDR

with Differential Input

TQ8224

PRELIMINARY DATA SHEET

Figure 1. TQ8224 Block Diagram

MODE0

MODE1

DEMUX

DIN

NDIN

DATINV

SLIP

Data

Regenerator

Parity

Generator

and

Output

(N)RQ1n-

(N)RQ2n

(N)RQPAR1-

(N)RQPAR2

PARSEL

RESET/RSTN

VOSC

Clock Input

Selector

CK311

NCK311

Clock Divider

VTUNE

NCLKIN

CLKIN

CLKSEL

VCO

CK155

CK78T

CK39

2.48832GHz

Active Clock

50Ω

Resistive

Tap

HCKOUT

PHREF

LOCKREF

DCREF

HINTCLK

PPMSEL

NRZ

Phase

Detector

and

LOCK

Detect

Charge

Pump

VTUNEO

PHADJ

LOCK

Internal PLL

TQ8224

PRELIMINARY DATA SHEET

Data Regeneration

The TQ8224 recovers and regenerates serial 2.48832

Gb/s data received at DIN and NDIN. The data recovery

can be optimized by adjusting the input data re-timing

clock phase at PHADJ. The PHADJ range is 2.5 +/-

0.5V. This corresponds to a centered sampling point

when PHADJ is 2.5V and a -128 pS or +128 pS offset

for 3V and 2V repectively. PHADJ must be externally

supplied. See the figure below.

selected if the CLKSEL is tied to VDD and the external

power supply pin, VOSC, is tied to VDD. CLKIN must be

tied to VEE through a 10kΩ resistor when the internal

clock is used.

The internal PLL is comprised of a NRZ phase detector,

a charge pump, and the internal VCO. This NRZ phase

detector’s phase error signals are integrated by the

Charge Pump block which then provides a VCO tune

voltage at VTUNEO. The Charge Pump block requires

external filter components which are connected at

VTUNEO. See Table 5 for loop filter values. The internal

PLL is completed by connecting VTUNEO to VTUNE.

The purpose of the internal PLL is to adjust the phase

of the internal VCO such that the negative edge of the

internal sampling clock is in the center of the data eye.

A phase offset can be added by adjusting the PHADJ

input voltage. A 38.88 MHz PECL clock must be

provided at HINTCLK to aid PLL acquisition.

The internal PLL provides an active high LOCK signal if

the frequency difference between the internal VCO and

the 38.88 MHz hint clock remains less than 488 ppm. If

the frequency difference becomes greater than 488

ppm then the LOCK signal deasserts low. The LOCK

signal will assert high when the frequency difference is

less then 122 ppm or 30 ppm. This hysteresis set point

is programmable and is determined by PPMSEL. When

PPMSEL is tied to VEE the LOCK set point is 30 ppm,

when PPMSEL is tied to VDD the LOCK set point is 122

ppm.

PHADJ Operation

PHADJ 3.0V

2.5V

2.0V

128pS

Time -128pS 0pS

The regenerated data is then re-synchronized by re-

timing it with the active 2.48832 GHz clock. (Negative

edge triggered sampling is used.)

The regenerated data can be inverted by tying the

DATINV pin to VEE. .

Bit Slipper

The TQ8224 can slip a bit on the incoming data stream.

An active low PECL pin, SLIP, causes the TQ8224 to

skip over one incoming data bit. This can be done for

framing purposes.

Timing Generation

The TQ8224 can receive an external 2.48832 GHz

(nominal) reference clock or generate a 2.48832 GHz

clock through an internal VCO. The output of the active

clock can be monitored at HKCOUT which provides a

30mV

output.

Internal Clock VCO and PLL

Figure 10 contains a reference diagram of operation

with the internal clock and PLL. The internal clock is

LOCK Signal Hysteresis

HIGH

LOCK

LOW

30ppm

488ppm

122ppm

Clock Freq. Difference

TELECOM

PRODUCTS

SONET/SDH/ATM

PRODUCTS

Function Description

TQ8224

PRELIMINARY DATA SHEET

Figure 2. PLL and Lock Detector Block Diagram

LOCKREF

PHASE

(N)DIN

2:1

VOSC

DETECT

CHARGE

PUMP

DOWN

VTUNEO

VTUNE

VCO

HCKOUT

HINTCLK

PHASE

FREQ

DETECT

2:1

PLLVDD

CLOCK

DIVIDER

LOCK

CK38

DETECT

External Clock VCO and PLL

See Figure 9 for a reference diagram of operation with

an external clock and PLL. The received clock can be

either single-ended or differential and is an AC coupled

input on CKIN and NCKIN. The external clock is

selected as the active clock if CLKSEL is tied to VEE.

VOSC and VTUNE must be tied to VEE when using an

external VCO. If the external clock is single ended the

unused input must be externally terminated through a

capacitor to an AC ground. The internal NRZ phase

detector generates PHREF and DCREF which, when

connected to an external integrator, may be used to

tune the external VCO.

Internal Clock VCO and External PLL

PHREF and DCREF must be connected to an external

integrator. The output of the integrator is then

connected to VTUNE, completing the PLL.

Functional Description

(continued)

TQ8224

PRELIMINARY DATA SHEET

The TQ8224 provides an internal Clock Divider which

frequency divides the active 2.48832 GHz clock

(internal or external source as selected by CLKSEL).

The output of the Clock Divider supplies the internal

clock signals necessary for the re-timing function and

demultiplexing function. The Clock Divider block also

outputs four external clocks: a differential 311.04 MHz

PECL clock at CK311 and NCK311, a 155.52MHz PECL

clock at CK155, a 77.76 MHz TTL clocks at CK78T, and

a 38.88 MHz PECL clock at CK39. Note that the clock

frequencies given above are dependant upon using the

part at 2.48832 GHz.

Data Demultiplexer and Parity Generator

The TQ8224 can be configured to run in one of three

modes. The demultiplexing modes are set by fixing the

MODE1 and MODE0 package pins according to the

following table.

MODE1

N.C.

VEE

MODE0

N.C.

VEE

Demultiplexing Mode

1:8

1:16

ALL 1’s OUTPUTS

In a 1:16 demultiplexing application, the TQ8224

regenerates the serial 2.48832 Gb/s data stream and

re-times it with the negative edge of the active 2.48832

Ghz clock. The re-timed serial data stream is then 1:16

demultiplexed by the DEMUX block into an 16-bit wide

155.52 MHz data bus at RQ11,NRQ11-RQ28,NRQ28. A

parity bit is generated for each byte, and transmitted in

parallel to the data at RQPAR1,NRQPAR1 and

RQPAR2,NRQPAR2. The 16-bit wide data plus two

parity bits are then clocked out on the rising edge of

the internally generated 155.52 MHz clock. See Figure

For all modes the first high speed input bit in time

appears on RQ11,NRQ11 which is the most significant

bit. Subsequent input data is output sequentially to

RQ12,NRQ12 through RQ28,NRQ28. Byte #1,

RQ11,NRQ11-RQ18,NRQ18 is the most significant

byte. Odd or even parity selection is programmable by

PARSEL. If PARSEL is left open (N.C.) the parity is

even. If PARSEL is tied to VEE the parity is odd.

In a 1:8 demultiplexing application, the TQ8224

regenerates the serial 2.48832 Gb/s data stream and

re-times it with the negative edge of the active 2.48832

Ghz clock. The re-timed serial data stream is then 1:8

demultiplexed by the DEMUX block into an 8-bit wide

TELECOM

PRODUCTS

SONET/SDH/ATM

PRODUCTS

Output Clocks

311.04 MHz data bus at RQ11,NRQ11-RQ18,NRQ18. A

parity bit is generated for each byte, and transmitted in

parallel to the data at RQPAR1,NRQPAR1. The 8-bit

wide data plus one parity bit are then clocked out on

the rising edge of the internally generated 311.04 MHz

clock. See Figure 6.

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