FINAL
Am29F010
1 Megabit (128 K x 8-bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— 5.0 V
±
10% for read, erase, and program
operations
— Simplifies system-level power requirements
s
High performance
— 45 ns maximum access time
s
Low power consumption
— 30 mA max active read current
— 50 mA max program/erase current
— <25
µA
typical standby current
s
Flexible sector architecture
— Eight uniform sectors
— Any combination of sectors can be erased
— Supports full chip erase
s
Sector protection
— Hardware-based feature that disables/re-
enables program and erase operations in any
combination of sectors
— Sector protection/unprotection can be
implemented using standard PROM
programming equipment
s
Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases the chip or any
combination of designated sector
— Embedded Program algorithm automatically
programs and verifies data at specified address
s
Minimum 100,000 program/erase cycles
guaranteed
s
Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
s
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s
Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
Publication#
16736
Rev:
G
Amendment/+2
Issue Date:
March 1998
GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 131,072 bytes. The Am29F010 is offered
in 32-pin PLCC, TSOP, and PDIP packages. The byte-
wide data appears on DQ0-DQ7. The device is de-
signed to be programmed in-system with the standard
system 5.0 Volt V
CC
supply. A 12.0 volt V
PP
is not re-
quired for program or erase operations. The device can
also be programmed or erased in standard EPROM
programmers.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus con-
tention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the pro-
gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This invokes the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The
hardware data protection
measures include a
low V
CC
detector automatically inhibits write operations
during power transitions. The
hardware sector pro-
tection
feature disables both program and erase oper-
ations in any combination of the sectors of memory,
and is implemented using standard EPROM program-
mers.
The system can place the device into the
standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e st l e ve l s o f q u a l i ty, re l i a b il i ty, a n d c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection.
2
Am29F010
FPGA/CPLD
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