CY7C346-25HC datasheet, PDF - EEWORLD Datasheet

CY7C346-25HC: DescriptionUV PLD, 52ns, 128-Cell, CMOS, CQCC84, WINDOWED, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size735KB，18 Pages; ManufacturerCypress Semiconductor

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CY7C346-25HC Overview

UV PLD, 52ns, 128-Cell, CMOS, CQCC84, WINDOWED, LCC-84

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	LCC
package instruction	WINDOWED, LCC-84
Contacts	84
Reach Compliance Code	not_compliant
Other features	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency	34.5 MHz
In-system programmable	NO
JESD-30 code	S-CQCC-J84
JESD-609 code	e0
JTAG BST	NO
length	29.21 mm
Dedicated input times	19
Number of I/O lines	48
Number of macro cells	128
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	19 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	WQCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER, WINDOW
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Programmable logic type	UV PLD
propagation delay	52 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	29.21 mm

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