CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379
for details.
6. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
7. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by trans conductance or r
DS(ON)
and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.
Boldface limits apply
over the operating junction temperature range, -40°C to +125°C.
T
J
= +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
J
= -40°C to +125°C
MIN
(Note 8)
MAX
(Note 8)
UNITS
DC Electrical Specifications
POWER SUPPLY
Voltage Range (Option A and B)
Voltage Range (Option C)
V
DD
Quiescent Current
V
DD
V
DD
I
DD
ENx = INx = GND
INA = INB = 1MHz, square wave
-
-
-
-
-
-
5
25
-
-
-
4.5
7.5
-
-
16
16
-
-
V
V
mA
mA
UNDERVOLTAGE
VDD Undervoltage Lock-out
(Options A and B) (Note 12,
Figure 9)
VDD Undervoltage Lock-out
(Option C) (Note 12, Figure 9)
Hysteresis (Option A or B)
Hysteresis (Option C)
V
UV
ENA = ENB = True
INA = INB = True
ENA = ENB = True
INA = INB = True (Note 9)
-
3.3
-
-
-
V
-
-
-
6.5
~25
~0.95
-
-
-
-
-
-
-
-
-
V
UV
V
mV
V
Submit Document Feedback
4
FN7707.4
September 30, 2015
ISL89163, ISL89164, ISL89165
V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified.
Boldface limits apply
over the operating junction temperature range, -40°C to +125°C. (Continued)
T
J
= +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
T
J
= -40°C to +125°C
MIN
(Note 8)
MAX
(Note 8)
UNITS
DC Electrical Specifications
INPUTS
Input Range
for INA, INB, ENA, ENB
Logic 0 Threshold
for INA, INB, ENA, ENB
(Note 11)
V
IN
Option A, B, or C
Option A, nominally 37% x 3.3V
V
IL
Option B, nominally 37% x 5.0V
Option C, nominally 20% x 12V
(Note 9)
Option A, nominally 63% x 3.3V
Logic 1 Threshold
for INA, INB, ENA, ENB
(Note 11)
Input Capacitance of INA, INB,
ENA, ENB (Note 10)
Input Bias Current
for INA, INB, ENA, ENB
V
IH
Option B, nominally 63% x 5.0V
Option C, nominally 80% x 12V
(Note 9)
C
IN
I
IN
GND < V
IN
< V
DD
-
-
-
-
-
-
-
-
-
-
1.22
1.85
2.4
2.08
3.15
9.6
2
-
-
-
-
-
-
-
-
-
-
GND
1.12
1.70
2.00
1.98
3.00
9.24
-
-10
V
DD
1.32
2.00
2.76
2.18
3.30
9.96
-
+10
V
V
V
V
V
V
V
pF
µA
OUTPUTS
High Level Output Voltage
Low Level Output Voltage
Peak Output Source Current
Peak Output Sink Current
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. The nominal 20% and 80% thresholds for option C are valid for any value within the specified range of VDD.
10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted
inputs is less than the logic 0 threshold voltage.
12. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9.
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