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MSM88SLI-85

Description
Standard SRAM, 8KX8, 85ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28
Categorystorage    storage   
File Size175KB,11 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

MSM88SLI-85 Overview

Standard SRAM, 8KX8, 85ns, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28

MSM88SLI-85 Parametric

Parameter NameAttribute value
MakerAPTA Group Inc
Parts packaging codeDIP
package instructionDIP,
Contacts28
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time85 ns
JESD-30 codeR-CDIP-T28
length35.56 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height4.45 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width15.24 mm
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
8K x 8 SRAM
MSM88 - 85/10
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 1.0 : February 2000
Description
The MSM88 is a Static RAM organised as 8K x 8
available with access times of 85 or 100ns. The
device is available in two ceramic package
options. It features completely static operation
with a low power standby mode and is 3.0V
battery back-up compatible. It is directly TTL
compatible and has common data inputs and
outputs.
The device may be screened in accordance with
MIL-STD-883.
8,192 x 8 CMOS Static RAM
Features
• Fast Access Times of 85 or 100 ns.
• JEDEC Standard footprint.
• Low Power Operation : 550 mW (max)
• Low Power Standby : 27.5 mW (max) -L version.
• Low Voltage Data Retention.
• Directly TTL compatible.
• Completely Static Operation.
Block Diagram
Pin Definitions
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6 TOP VIEW
7
S
8 PACKAGE
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CS2
A8
A9
A11
OE
A10
CS1
D7
D6
D5
D4
D3
A3
A4
A5
A6
A7
A8
A12
X ADDRESS BUFFER
ROW DECODER
65,536
BIT
MEMORY
ARRAY
D0
D7
/WE
/OE
/CS1
CS2
I/O
BUFFER
COLUMN I/O
COLUMN DECODER
Y ADDRESS BUFFER
A11
A10
A9
A2
A1
A0
Package Details
Pin Count
28
Description
0.6"Dual-in-Line (DIP)
Package Type
S
Pin Functions
A0~A12
Address inputs
D0-7
Data Input/Output
CS1, CS2
Chip Selects
OE
Output Enable
WE
Write Enable
V
CC
Power(+5V)
GND
Ground
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