IDT72203L25TDB datasheet, PDF - EEWORLD Datasheet

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IDT72203L25TDB: DescriptionFIFO, 256X1, 15ns, Synchronous, CMOS, CDIP24, 0.300 INCH, THIN, CERDIP-24; Categorystorage storage; File Size187KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72203L25TDB Overview

FIFO, 256X1, 15ns, Synchronous, CMOS, CDIP24, 0.300 INCH, THIN, CERDIP-24

IDT72203L25TDB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	DIP
package instruction	0.300 INCH, THIN, CERDIP-24
Contacts	24
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	15 ns
Maximum clock frequency (fCLK)	40 MHz
period time	25 ns
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
length	32.004 mm
memory density	256 bit
Memory IC Type	OTHER FIFO
memory width	1
Number of functions	1
Number of terminals	24
word count	256 words
character code	256
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	256X1
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	SERIAL
power supply	5 V
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum standby current	0.1 A
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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IDT72423/72203/72213 CMOS SINGLE BIT SyncFIFO™

64 x 1, 256 x 1, 512 x 1

CMOS SINGLE BIT SyncFIFO

64 X 1, 256 x 1, 512 x 1

™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRELIMINARY

IDT72423

IDT72203

IDT72213

Integrated Device Technology, Inc.

FEATURES:

64 x 1-bit organization (IDT72423)

256 x 1-bit organization (IDT72203)

512 x 1-bit organization (IDT72213)

10 ns read/write cycle time (IDT72423/72203/72213)

Independent read and write clock lines

Empty and Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can

be programmed to any depth via a dedicated port (Pn).

These flags default to Empty+7 and Full-7, respectively.

• Output enable puts output data bus in high impedance

state

• Available in 24-pin SOIC, 24-pin plastic DIP (300 mil.),

and 24-pin ceramic DIP (300 mil.)

• Military product compliant to MIL-STD-883, Class B

Advanced submicron CMOS technology

•

DESCRIPTION:

The IDT72423/72203/72213 SyncFIFO

™

are very high-

speed, low-power First-In, First-Out (FIFO) memories with a

word width of 1 and clocked read and write controls. The

IDT72423/72203/72213 have a 64, 256, and 512 x 1-bit

memory arrays, respectively. These FIFOs are appropriate

for a wide variety of serial data buffering needs, especially

telecommunications applications such as networks, modems,

signal processing, and serial interfaces.

These single-bit FIFOs have 1-bit input (D) and output ports

(Q).The input port is controlled by a free-running clock (WCLK),

and two write enable pins (

WEN1

, WEN2). Data is written into

the Synchronous FIFO on every rising clock edge when the

write enable pins are asserted. The output port is controlled by

another clock pin (RCLK) and a read enable pin (

REN

). The

read clock can be tied to the write clock for single clock

operation or the two clocks can run asynchronous of one

another for dual clock operation. An output enable pin (

) is

provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (

)

and Full (

). Two programmable flags, Almost-Empty (

PAE

)

and Almost-Full (

PAF

), are provided for improved system

control. The programmable flags default to Empty+7 and Full-

7 for

PAE

and

PAF

, respectively. The programmable flag

offset is loaded via the Program Inputs (P0 - P7), on the rising

WCLK when the load pin (

) is asserted.

The IDT72423/72203/72213/ are fabricated using IDT’s

high-speed submicron CMOS technology. Military grade prod-

uct is manufactured in compliance with the latest revision of

MIL-STD-883, Class B.

- P

FUNCTIONAL BLOCK DIAGRAM

WCLK

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

64 x 1

256 x 1

512 x 1

FLAG

LOGIC

PAE

PAF

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

RESET LOGIC

OUTPUT REGISTER

RCLK

REN

3111 drw 01

The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc

MAY 1994

DSC-2065/-

5.04

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