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UPD720100AGM-8ED

Description
USB Bus Controller, MOS, PQFP160, 24 X 24 MM, PLASTIC, LQFP-160
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size315KB,32 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPD720100AGM-8ED Overview

USB Bus Controller, MOS, PQFP160, 24 X 24 MM, PLASTIC, LQFP-160

UPD720100AGM-8ED Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNEC Electronics
Parts packaging codeQFP
package instructionLFQFP,
Contacts160
Reach Compliance Codecompliant
ECCN code3A001.A.3
Address bus width32
Bus compatibilityPCI
maximum clock frequency48 MHz
External data bus width32
JESD-30 codeS-PQFP-G160
JESD-609 codee0
length24 mm
Number of terminals160
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24 mm
uPs/uCs/peripheral integrated circuit typeBUS CONTROLLER, UNIVERSAL SERIAL BUS

UPD720100AGM-8ED Preview

DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD720100A
USB2.0 HOST CONTROLLER
The
µ
PD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The
µ
PD720100A is integrated three host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µ
PD720100A User’s Manual: S15534E
FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI
host controller core for high-speed signaling.
• Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
• Supports PCI Mobile Design Guide Revision 1.1.
• Supports PCI-Bus Power Management Interface Specification release 1.1.
• PCI Bus bus-master access
• System clock is generated by 30 MHz X’tal or 48 MHz clock input.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
Package
160-pin plastic LQFP (Fine pitch) (24
×
24)
160-pin plastic LQFP (Fine pitch) (24
×
24)
176-pin plastic FBGA (15
×
15)
µ
PD720100AGM-8ED
µ
PD720100AGM-8EY
µ
PD720100AS1-2C
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15535EJ2V0DS00 (2nd edition)
Date Published October 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
©
2001
µ
PD720100A
BLOCK DIAGRAM
PCI Bus
PME0
INTA0
INTB0
INTC0
PCI Bus Interface
WakeUp_Event
WakeUp_Event
WakeUp_Event
Arbiter
OHCI
Host
Controller
#1
OHCI
Host
Controller
#2
EHCI
Host
Controller
SMI0
Root Hub
PHY
Port 1
Port 2
Port 3
Port 4
Port 5
USB Bus
2
Data Sheet S15535EJ2V0DS
µ
PD720100A
PCI Bus Interface
:handles 32-bits 33 MHz PCI Bus master and target function which comply with PCI
specification release 2.2. The number of enabled ports are set by bit in configuration
space.
Arbiter
OHCI Host Controller #1
OHCI Host Controller #2
EHCI Host Controller
Root Hub
PHY
INTA0
INTB0
INTC0
SMI0
:arbitrates among two OHCI Host controller cores and one EHCI Host controller core.
:handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.
:handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.
:handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.
:handles USB hub function in Host controller and controls connection (routing)
between Host controller core and port.
:consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
etc
:is the PCI interrupt signal for OHCI Host Controller #1.
:is the PCI interrupt signal for OHCI Host Controller #2.
:is the PCI interrupt signal for EHCI Host Controller.
:is the interrupt signal which is specified by Open Host Controller Interface
Specification for USB Rev 1.0a. The SMI signal of each OHCI Host Controller
appears at this signal.
PME0
:is the interrupt signal which is specified by PCI-Bus Power Management Interface
Specification release 1.1. Wakeup signal of each host controller core appears at this
signal.
Data Sheet S15535EJ2V0DS
3
µ
PD720100A
PIN CONFIGURATION
160-pin plastic LQFP (Fine pitch) (24
×
24)
µ
PD720100AGM-8ED
µ
PD720100AGM-8EY
Top View
V
SS
V
SS
RSDP4
DP4
V
DD
DM4
RSDM4
V
SS
RSDP3
DP3
V
DD
DM3
RSDM3
V
SS
V
DD
AV
SS
RREF
AV
SS
(R)
AV
DD
N.C.
PC1
AV
SS
PC2
AV
DD
AV
SS
V
DD
V
SS
RSDP2
DP2
V
DD
DM2
RSDM2
V
SS
RSDP1
DP1
V
DD
DM1
RSDM1
V
SS
V
SS
150
140
130
160
155
V
DD
NTEST1
NTEST2
TEST
XT1/SCLK
XT2
LEGC
V
DD
V
SS
VCCRST0
SMI0
IRI1
IRI2
IRO1
IRO2
A20S
PME0
PCLK
VBBRST0
V
DD
V
SS
V
DD_PCI
INTA0
INTB0
INTC0
PIN_EN
GNT0
REQ0
AD31
AD30
V
SS
AD29
AD28
AD27
AD26
AD25
AD24
CBE30
IDSEL
V
DD
145
135
125
121
1
120
5
115
10
110
15
105
20
100
25
95
30
90
35
85
40
81
60
65
70
41
45
4
V
SS
V
SS
AD23
SMC
SIN/TIN
SOT/TOUT
AD22
AD21
AD20
AD19
V
DD
AD18
AD17
AD16
CBE20
FRAME0
IRDY0
TRDY0
DEVSEL0
V
DD_PCI
STOP0
PERR0
SERR0
PAR
CBE10
V
SS
AD15
AD14
AD13
V
DD
AD12
AD11
AD10
AD9
AD8
CBE00
AD7
AD6
V
SS
V
SS
50
Data Sheet S15535EJ2V0DS
55
75
80
V
DD
SELCLK
N.C.
SELDAT
V
SS
RSDP5
DP5
V
DD
DM5
RSDM5
V
SS
CLKSEL
V
SS
PPON5
TEB
PPON4
SCK/TCLK
PPON3
PPON2
V
SS
V
DD
OCI3
AMC
OCI4
OCI2
OCI5
PPON1
OCI1
SRMOD
SRCLK
SRDTA
V
DD_PCI
CRUN0
AD0
AD1
AD2
AD3
AD4
AD5
V
DD
µ
PD720100A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
V
DD
NTEST1
NTEST2
TEST
XT1/SCLK
XT2
LEGC
V
DD
V
SS
VCCRST0
SMI0
IRI1
IRI2
IRO1
IRO2
A20S
PME0
PCLK
VBBRST0
V
DD
V
SS
V
DD_PCI
INTA0
INTB0
INTC0
PIN_EN
GNT0
REQ0
AD31
AD30
V
SS
AD29
AD28
AD27
AD26
AD25
AD24
CBE30
IDSEL
V
DD
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
V
SS
V
SS
AD23
SMC
SIN/TIN
SOT/TOUT
AD22
AD21
AD20
AD19
V
DD
AD18
AD17
AD16
CBE20
FRAME0
IRDY0
TRDY0
DEVSEL0
V
DD_PCI
STOP0
PERR0
SERR0
PAR
CBE10
V
SS
AD15
AD14
AD13
V
DD
AD12
AD11
AD10
AD9
AD8
CBE00
AD7
AD6
V
SS
V
SS
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Pin Name
V
DD
AD5
AD4
AD3
AD2
AD1
AD0
CRUN0
V
DD_PCI
SRDTA
SRCLK
SRMOD
OCI1
PPON1
OCI5
OCI2
OCI4
AMC
OCI3
V
DD
V
SS
PPON2
PPON3
SCK/TCLK
PPON4
TEB
PPON5
V
SS
CLKSEL
V
SS
RSDM5
DM5
V
DD
DP5
RSDP5
V
SS
SELDAT
N.C.
SELCLK
V
DD
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Pin Name
V
SS
V
SS
RSDM1
DM1
V
DD
DP1
RSDP1
V
SS
RSDM2
DM2
V
DD
DP2
RSDP2
V
SS
V
DD
AV
SS
AV
DD
PC2
AV
SS
PC1
N.C.
AV
DD
AV
SS
(R)
RREF
AV
SS
V
DD
V
SS
RSDM3
DM3
V
DD
DP3
RSDP3
V
SS
RSDM4
DM4
V
DD
DP4
RSDP4
V
SS
V
SS
Remark
AV
SS
(R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ.
Data Sheet S15535EJ2V0DS
5
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