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SN54ABTH162245, SN74ABTH162245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999
D
D
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
™
Family
A-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
State-of-the-Art
EPIC-
ΙΙ
B
™
BiCMOS Design
Significantly Reduces Power Dissipation
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25°C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and Shrink
Small-Outline (DL) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54ABTH162245 . . . WD PACKAGE
SN74ABTH162245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
description
The ’ABTH162245 devices are 16-bit noninverting 3-state transceivers designed for synchronous two-way
communication between data buses. The control-function implementation minimizes external timing
requirements.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors
to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH162245 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABTH162245 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
©
1999, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1
SN54ABTH162245, SN74ABTH162245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
L
L
H
DIR
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
logic symbol
†
48
1OE
1DIR
1
25
2OE
2DIR
24
G3
3 EN1 [BA]
3 EN2 [AB]
G6
6 EN4 [BA]
6 EN5 [AB]
1A1
47
1
2
2
1B1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
46
44
43
41
40
38
37
36
4
3
5
6
8
9
11
12
13
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
35
33
32
30
29
27
26
5
14
16
17
19
20
22
23
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
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•
DALLAS, TEXAS 75265
SN54ABTH162245, SN74ABTH162245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999
logic diagram (positive logic)
1DIR
1
2DIR
48
24
1OE
25
2OE
1A1
47
2A1
36
2
1B1
13
2B1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V
O
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, I
O
: SN54ABTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABTH162245 (B port) . . . . . . . . . . . . . . . . . . . . . . . 128 mA
SN54/74ABTH162245 (A port) . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ABTH162245, SN74ABTH162245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS712A – FEBRUARY 1998 – REVISED APRIL 1999
recommended operating conditions (see Note 3)
SN54ABTH162245
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level
High level output current
Low-level
Low level output current
Input transition rise or fall rate
B port
A port
B port
A port
Outputs enabled
0
4.5
2
0.8
VCC
–24
–12
48
12
10
0
MAX
5.5
SN74ABTH162245
MIN
4.5
2
0.8
VCC
–32
–12
64
12
10
MAX
5.5
UNIT
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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•
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