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935283049118

Description
8 I/O, PIA-GENERAL PURPOSE, PQCC16
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size585KB,35 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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935283049118 Overview

8 I/O, PIA-GENERAL PURPOSE, PQCC16

935283049118 Parametric

Parameter NameAttribute value
MakerNXP
package instructionHVQCCN,
Reach Compliance Codeunknown
ECCN codeEAR99
JESD-30 codeS-PQCC-N16
length3 mm
Number of I/O lines8
Number of ports1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Maximum seat height1 mm
Maximum supply voltage5.5 V
Minimum supply voltage2.3 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
width3 mm
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
PCA9554; PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
Rev. 9 — 19 March 2013
Product data sheet
1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I
2
C-bus I/O expanders.
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, and so on.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I
2
C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in
Application Note AN469.
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I
2
C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I
2
C-bus/SMBus.
2. Features and benefits
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
8 I/O pins which default to 8 inputs
0 Hz to 400 kHz clock frequency

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