PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Features
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal
• Five PCIe
®
Gen. 2 100MHz HCSL outputs with optional
-0.5% spread spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
Description
The PI6C49003A is a clock generator device intended for PCIe
®
Gen2 networking applications. The device includes five 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe Gen
2, two single-ended 50MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133MHz output.
Using a serially programmable SMBUS interface, the PI6C49003A
incorporates spread spectrum modulation on the twelve 100MHz
HCSL PCIe Gen 2 outputs, and independent frequency margining
on the 50MHz output, 33.3333MHz and 66.6666MHz clock
outputs.
Block Diagram
VDD
14
Pin Configuration
VDD
IREF
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
VDD
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
GND
VDD
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
VDD
GND
VDD
100M_Q4+
100M_Q4-
33/66/133M_Out1
VDD
GND
VDD
X2
X1
25 MHz
crystal or
clock input
Clock Buffer/
Crystal
Oscillator
5
VDD
100M_OUT(0-4)
VDD
GND
50M_OUT(1-2)
PLL, Dividers,
Buffers, and
Logic
GND
VDD
33/66/133M_OUT1
GND
VDD
SCLK
SDATA
PD_RESET
32.256M_OUT1
SCLK
SDATA
GND
50M_Out1
50M_Out2
10
GND
ISET
475 Ohms
1%
VDD
GND
VDD
32.256M_Out1
GND
NC
NC
PD_RESET
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11/11/14
PI6C49003A
PCIe® Gen 2
Networking Clock Generator
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Name
V
DD
IREF
NC
NC
V
DD
V
DD
GND
GND
V
DD
GND
V
DD
SCLK
SDATA
GND
50M_Out1
50M_Out2
V
DD
GND
V
DD
32.256M_Out1
GND
NC
NC
Power
Power
Power
Power
Power
Power
Power
Input
I/O
Power
Output
Output
Power
Power
Power
Output
Power
Pin Type
Power
Output
Pin Description
3.3V Supply Pin
Connect to 475-Ohm resistor to set HCSL output drive current
No connect. Leave open
No connect. Leave open
3.3V Supply Pin
3.3V Supply Pin
Ground
Ground
3.3V Supply Pin
Ground
3.3V Supply Pin
SMBus compatible input clock. Supports fast mode 400kHz input clock.
SMBus compatible data line
Ground
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
3.3V Supply Pin
Ground
3.3V Supply Pin
32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal
110k-Ohm pull-down.
Ground
PD_RESET
X1
X2
V
DD
GND
V
DD
33/66/133M_Out1
100M_Q4-
100M_Q4+
Input
Input
Output
Power
Power
Power
Output
Output
Output
Power down reset - when low all PLL's are powered down and outputs tristated.
SMBus registers are reset to default values.
Crystal input. Integrated 6pF capacitance
Crystal output. Integrated 6pF capacitance
3.3V Supply Pin
Ground
3.3V Supply Pin
33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has
a nominal 110k-Ohm pull-down.
100MHz HCSL output
100MHz HCSL output
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PI6C49003A
PCIe® Gen 2
Networking Clock Generator
Pin Description (Cont..)
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Name
V
DD
GND
V
DD
100M_Q3-
100M_Q3+
100M_Q2-
100M_Q2+
V
DD
GND
V
DD
100M_Q1-
100M_Q1+
100M_Q0+
100M_Q0-
V
DD
GND
Pin Type
Power
Power
Power
Output
Output
Output
Output
Power
Power
Power
Output
Output
Output
Output
Power
Power
Pin Description
3.3V Supply Pin
Ground
3.3V Supply Pin
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
Ground
3.3V Supply Pin
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
Ground
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11/11/14
PI6C49003A
PCIe® Gen 2
Networking Clock Generator
50MHz Frequency Margining Table
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50M_OUT1, 50M_OUT2
nominal
nominal + 1%
nominal + 2%
nominal + 3%
nominal + 4%
nominal + 5%
nominal + 6%
nominal + 8%
nominal + 10%
nominal - 1%
nominal - 2%
nominal - 3%
nominal - 4%
nominal - 6%
nominal - 8%
nominal - 10%
33/66/133MHz Frequency Margining
Table
FS6
0
0
0
0
1
1
1
1
FS5
0
0
1
1
0
0
1
1
FS4
0
1
0
1
0
1
0
1
33M/66M/133M_OUT1
33.3333MHz
66.6666MHz +2%
66.6666MHz +1%
66.6666MHz +0%
66.6666MHz -2%
66.6666MHz -4%
66.6666MHz -6%
133.3333MHz
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11/11/14
PI6C49003A
PCIe® Gen 2
Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49003A is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
1
How to Write
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
W/R
0/1
1 bit
Start
bit
8 bits
D2H
1
Ack
8 bits
Register
offset
1
Ack
8 bits
Byte Count
=N
1
Ack
8 bits
Data Byte
0
1
Ack
…
8 bits
Data Byte
N-1
1
Ack
1 bit
Stop bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read
(M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
1 bit
8 bits
1 bit
8 bits
1 bit
1 bit
8 bits
1 bit
8 bits
S:
sends #
of data
bytes
that
will be
sent: X
1 bit
8 bits
S:
sends
start-
ing
data
byte
N
1 bit
…
8 bits
1 bit
1 bit
M:
Start
bit
M: Send
"D2h"
S:
sends
Ack
M: send
starting
databyte
location:
N
S:
sends
Ack
M:
Start
bit
M:
Send
"D3h"
S:
sends
Ack
M:
sends
Ack
M:
sends
Ack
…
S:
sends
data
byte
N+X-1
M: Not
Ac-
knowl-
edge
M:
Stop
bit
Byte 0: Spread Spectrum Control Register
Bit
7
6
Description
Spread Spectrum Selection for 100MHz HCSL PCI-
Express clocks
Enables hardware or software control of OE bits (see
Byte 0–Bit 6 and Bit 5 Functionality table)
Software PD_RESET bit. Enables or disables all out-
puts
(see Byte 0–Bit 6 and Bit 5 Functionality table)
Frequency margining select bit FS3
Frequency margining select bit FS2
Frequency margining select bit FS1
Frequency margining select bit FS0
OE for single-ended 50MHz output 50M_Out2
Type
RW
RW
Power Up
Condition
0
0
Output(s)
Affected
All 100MHz HCSL
PCI Express outputs
PD_RESET pin, bit 5
Notes
0=spread off
1 = -0.5% down spread
0 = hardware cntl
1 = software ctrl
0 = disabled
1 = enabled
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
1
1
0
1
0
1
All outputs
50M_Out1 and 50M_
Out2
See 50MHz Frequency
Margining Table on
Page 3
0 = disabled
1 = enabled
11/11/14
Single-ended 50MHz
output 50M_Out2
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