Integrated
Circuit
Systems, Inc.
ICS952606
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 48-pin part
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
1 - 0.7V current-mode differential CPU pairs for ITP
•
1 - 0.7V current-mode differential SRC pair
•
9 - PCI (33MHz)
•
1 - USB, 48MHz
•
1 - DOT, 48MHz
•
2 - REF, 14.318MHz
•
3 - 3V66, 66.66MHz
•
1 - 3V66/VCH, selectable 48MHz or 66MHz
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA
•
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
•
•
•
Supports CPU clks up to 400MHz in test mode
Uses external 14.318MHz crystal
Supports undriven differential CPU, SRC pair in PD#
for power management.
Key Specifications:
•
CPU/SRC outputs cycle-cycle jitter < 125ps
•
3V66 outputs cycle-cycle jitter < 250ps
•
•
•
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Pin Configuration
Functionality
U
SB/
FS2
CPU
SRC
3V66
PCI
REF
DOT
MHz
B6b5 FS_A FS_B MHz
MHz
MHz MHz
MHz
0
0
100.00 100/200 66.66 33.33 14.318 48.00
0
1
200.00 100/200 66.66 33.33 14.318 48.00
0
1
0
133.33 100/200 66.66 33.33 14.318 48.00
1
1
166.66 100/200 66.66 33.33 14.318 48.00
0
0
200.00 100/200 66.66 33.33 14.318 48.00
0
1
400.00 100/200 66.66 33.33 14.318 48.00
1
1
0
266.66 100/200 66.66 33.33 14.318 48.00
1
1
333.33 100/200 66.66 33.33 14.318 48.00
*FSA/REF0
*FSB/REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PD#
48MHz_DOT
48MHz_USB
GND
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GND
IREF
CPUCLKT_ITP
CPUCLKC_ITP
GND
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GND
SRCCLKT
SRCCLKC
VDD
Vtt_Pwrgd#
SDATA
SCLK
3V66_0
3V66_1
GND
VDD3V66
3V66_2
3V66_3/VCH
**120KW pull-down
48-pin SSOP
0717F—06/10/05
ICS952606
Integrated
Circuit
Systems, Inc.
ICS952606
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
*FSA/REF0
*FSB/REF1
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PD#
48MHz_DOT
48MHz_USB
GND
VDD48
PIN TYPE
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Asynchronous active low input pin, with 120Kohm internal pull-up
resistor, used to power down the device. The internal clocks are
disabled and the VCO and the crystal are stopped.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
0717F—06/10/05
2
Integrated
Circuit
Systems, Inc.
ICS952606
Pin Description (Continued)
PIN #
30
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
3V66_0
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
SDATA
Vtt_Pwrgd#
VDD
SRCCLKC
SRCCLKT
GND
CPUCLKC0
CPUCLKT0
VDDCPU
CPUCLKC1
CPUCLKT1
GND
CPUCLKC_ITP
CPUCLKT_ITP
PIN TYPE
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
DESCRIPTION
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
3.3V power for the PLL core.
46
47
48
IREF
GND
VDDA
OUT
PWR
PWR
0717F—06/10/05
3
Integrated
Circuit
Systems, Inc.
ICS952606
General Description
ICS952606
is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single
chip solution for next generation P4 Intel processors and Intel chipsets.
ICS952606
is driven with a 14.318MHz crystal. It
generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
PLL2
Frequency
Dividers
48MHz, USB, DOT, VCH
X1
X2
XTAL
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT0
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
SRCCLKC0
3V66(3:0)
PCICLK_F (2:0)
SCLK
SDATA
VTTPWRGD#
PD#
FS_A
FS_B
Control
Logic
PCICLK (5:0)
CPUCLKT_ITP
CPUCLKC_ITP
I REF
Power Groups
Pin Number
VDD
GND
3
6
27
28
10,16
11,17
34
37
48
47
24
23
--
47
40
43
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, Fix Digital, Fix Analog
IREF
CPUCLK clocks
0717F—06/10/05
4
Integrated
Circuit
Systems, Inc.
ICS952606
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
-0.5
-65
0
Max
V
DD +
0.5V
V
DD +
0.5V
150
70
115
Units
V
V
°C
°C
°C
V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Powerdown Current
Input Frequency
3
Pin Inductance
1
1
CONDITIONS
3.3V +/-5%
3.3V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-up
resistors
V
IN
= 0 V; Inputs with pull-up
resistors
Full Active, C
L
= Full load;
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
MIN
2
V
SS
-
0.3
-5
-5
-200
TYP
MAX
V
DD
+ 0.3
0.8
5
UNITS NOTES
V
V
uA
uA
uA
I
DD3.3OP
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
260.000
31.000
0.300
14.31818
350
35
12
7
5
6
5
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
us
ns
ns
Logic Inputs
Output pin capacitance
Input Capacitance
X1 & X2 pins
From VDD Power-Up or de-
T
STAB
1.8
Clk Stabilization
1,2
assertion of PD# to 1st clock.
Triangular Modulation
30
33
Modulation Frequency
CPU output enable after
Tdrive_PD#
300
PD# de-assertion
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
3
1
1
1
1
1,2
1
1
1
2
0717F—06/10/05
5
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