TECHNICAL
MANUAL
L80227
10BASE-T/
100BASE-TX
Ethernet PHY
October 2002
®
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
DB14-000139-02, Third Edition (October 2002)
This document describes revision/release 2 of LSI Logic Corporation’s
10BASE-T/100BASE-TX Ethernet PHY and will remain the official reference
source for all revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic and the LSI Logic logo design are trademarks or registered trademarks
of LSI Logic Corporation. All other brand and product names may be trademarks
of their respective companies.
MT
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html
ii
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the L80227
10BASE-T/100BASE-TX Ethernet Physical Layer Device (PHY). It
contains a complete functional description for the device and includes
complete physical and electrical specifications for the product.
Audience
This document assumes that you have some familiarity with Ethernet
devices and related support devices. The people who benefit from this
book are:
•
•
Organization
Engineers and managers who are evaluating the device for possible
use in a system
Engineers who are designing the device into a system
This document has the following chapters:
•
•
•
•
•
Chapter 1,
Introduction,
describes the device in general terms and
gives a block diagram and lists the device features.
Chapter 2,
Functional Description,
describes each of the internal
blocks in the device in some detail.
Chapter 3,
Signal Descriptions,
lists and describes the device input
and output signals.
Chapter 4,
Registers,
gives a register summary and describes each
of the bits in each register.
Chapter 5,
Management Interface,
describes the device
Management Interface, which allows the registers to be read and
written.
L80227 10BASE-T/100BASE-TX Ethernet PHY Technical Manual
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
iii
•
•
Chapter 6,
Specifications,
lists the AC and DC characteristics and
gives typical timing parameters.
Appendix A,
Application Information,
gives practical guidelines for
incorporating the device into a design.
Abbreviations Used in This Manual
Below is a list of abbreviations used throughout this manual.
100BASE-T
10BASE-T
4B5B
CLK
CRC
CRS
CSMA
CWRD
DA
ECL
EOF
ESD
FCS
FDX
FEF
FIFO
FLP
FX
HDX
HIZ
I/G
IETF
IPG
IREF
L/T
LSB
MIB
MLT3
ms
MSB
mV
NLP
NRZI
NRZ
OP
PCB
pF
100 Mbit/s Twisted-Pair Ethernet
10 Mbit/s Twisted-Pair Ethernet
4-Bit 5-Bit
Clock
Cyclic Redundancy Check
Carrier Sense
Carrier Sense Multiple Access
Codeword
Destination Address
Emitter-Coupled Logic
End of Frame
End of Stream Delimiter
Frame Check Sequence
Full-Duplex
Far End Fault
First In - First Out
Fast Link Pulse
Fiber
Half-Duplex
High Impedance
Individual/Group
Internet Engineering Task Force
Inter-Packet Gap
Reference Current
Length and Type
Least-Significant Bit
Management Information Base
Multi-Level Transmission (3 levels)
millisecond
Most-Significant Bit
millivolt
Normal Link Pulse
Non-Return to Zero Inverted
Non-Return to Zero
Opcode
Printed Circuit Board
picofarad
iv
Preface
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
PRE
R/LH
R/LHI
R/LL
R/LLI
R/LT
R/LTI
R/WSC
RFC
RJ-45
RMON
SA
SFD
SNMP
SOI
SSD
STP
TP
µH
µP
UTP
Preamble
Read Latched High
Read Latched High with Interrupt
Read Latched Low
Read Latched Low with Interrupt
Read Latched Transition
Read Latched Transition with Interrupt
Read/Write Self Clearing
Request for Comments
Registered Jack-45
Remote Monitoring
Start Address or Station Address
Start of Frame Delimiter
Simple Network Management Protocol
Start of Idle
Start of Stream Delimiter
Shielded Twisted Pair
Twisted Pair
microhenry
microprocessor
Unshielded Twisted Pair
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is
italicized.
The word
assert
means to drive a signal true or active. The word
deassert
means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Preface
Copyright © 2000, 2001, 2002 by LSI Logic Corporation. All rights reserved.
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