PRELIMINARY
W9864G6EB
1M
×
4 BANKS
×
16 BITS SDRAM
GENERAL DESCRIPTION
W9864G6EB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.13
µm
process technology,
W9864G6EB delivers a data bandwidth of up to 286M bytes per second (-7). The -7 parts can run up
to 143MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9864G6DB is ideal for main memory in
high performance applications.
.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7V ~3.6V power supply
1048576 words
×
4 banks
×
16 bits organization
Self Refresh Current: Standard and Low Power
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Package: BGA 60 balls pitch=0.6
using PB free materials
AVAILABLE PART NUMBER
PART NUMBER
W9864G6EB-7
W9864G6EB-7L
SPEED (CL = 3)
143 MHz
143 MHz
SELF REFRESH
CURRENT (MAX.)
1 mA
400
µA
OPERATING
TEMPERATURE
0°C ~ 70°C
0°C ~ 70°C
Publication Release Date: August 1,2003
Revision P02
-1-
W9864G6EB
PIN CONFIGURATION
Top View
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
VSS
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
VSS
UDQM
CLK
NC
A9
A7
A5
A4
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
VDD
LDQM
RAS#
NC
BS1
A0
A2
A3
6 7
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
CAS#
CS#
BS0
A10
A1
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
Bottom View
7 6
2 1
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
VDD
LDQM
RAS#
NC
BS1
A0
A2
A3
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
VSS
UDQM
CLK
NC
A9
A7
A5
A4
VSS
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
VSS
CAS#
CS#
BS0
A10
A1
VDD
-2-
W9864G6EB
PIN DESCRIPTION
BALL LOCATION PIN NAME
M1,M2,N1,N2,N6, A0−A11
N7,P1,P2,P6,P7,R
6,
FUNCTION
Address
DESCRIPTION
Multiplexed pins for row and column address. Row
address: A0−A11. Column address: A0−A7. A10 is
sampled during a precharge command to determine
if all banks are to be precharged or bank selected by
BS0, BS1.
Select bank to activate during row address latch
time, or bank to read/write during address latch time.
Multiplexed pins for data output and input.
M6,M7
BS0, BS1
Bank Select
A2,A6,B1,B7,C1,C DQ0−DQ1 Data Input/
Output
7,D1,D2,D6,D7,E1, 5
E7,F1,F7,G1,G7
L7
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock
RAS
,
CAS
and
WE
define the
operation to be executed.
K6
RAS
Row Address
Strobe
K7
J7
J2,J6
CAS
WE
Column
Referred to
RAS
Address Strobe
Write Enable
Input/output
mask
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from VDD, to improve DQ noise
immunity.
Separated ground from V
SS
, to improve DQ noise
immunity.
No connection
UDQM
LDQM
K2
L1
CLK
CKE
Clock Inputs
Clock Enable
A7,H6,R7
A1,H2,R1
B6,C2,E6,F2
B2,C6,E2,F6
VDD
V
SS
VDD
Q
V
SSQ
Power (+3.3V)
Ground
Power (+3.3V)
for I/O buffer
Ground for I/O
buffer
No Connection
G2,G6,H1,H7,J1,K NC
1,L2,L6
-3-
Publication Release Date: August 1,2003
Revision P02
W9864G6EB
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
CAS
GENERATOR
COMMAND
DECODER
WE
ROW DECODER
COLUMN DECODER
COLUMN DECODER
ROW DECODER
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A0
A9
A11
BS0
BS1
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN
COUNTER
DQ
BUFFER
DQ0
DQ15
REFRESH
COUNTER
UDQM
LDQM
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 256 * 16
-4-
W9864G6EB
FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all V
CC
and V
CCQ
pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the "NOP" state. The power up voltage must not exceed V
CC
+0.3V
on any of the input pins or V
CC
supplies. After power up, an initial pause of 200
µS
is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also
required before or after programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of
RAS
,
CAS
,
CS
and
WE
at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to t
RSC
has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (t
RCD
). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t
RC
).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and
vice versa) is the Bank to Bank delay time (t
RRD
). The maximum time that each bank can be held
active is specified as T
RAS
(max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by
setting
RAS
high and
CAS
low at the clock rising edge after minimum of t
RCD
delay.
WE
pin
voltage level defines whether the access cycle is a read operation (
WE
high), or a write operation
(
WE
low). The address inputs determine the starting column address. Reading or writing to a
different row within an activated bank requires the bank be precharged and a new Bank Activate
command be issued. When more than one bank is activated, interleaved bank Read or Write
operations are possible. By using the programmed burst length and alternating the access and
precharge operations between multiple banks, seamless data access operation among many different
pages can be realized. Read or Write Commands can also be issued to the same bank or between
active banks on every clock cycle.
Publication Release Date: August 1,2003
Revision P02
-5-
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