8624BYLFT datasheet, PDF - EEWORLD Datasheet

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8624BYLFT: DescriptionTQFP-32, Reel; Categorylogic logic; File Size263KB，19 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8624BYLFT Overview

TQFP-32, Reel

8624BYLFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LQFP, QFP32,.35SQ,32
Contacts	32
Manufacturer packaging code	PRG32
Reach Compliance Code	compliant
ECCN code	EAR99
series	8624
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G32
JESD-609 code	e3
length	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	5
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	1.8,3.3 V
Prop。Delay @ Nom-Sup	4.4 ns
propagation delay (tpd)	4.4 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.025 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm
minfmax	31.25 MHz

8624BYLFT Preview

Low Skew, 1-to-5 Differential-to-HSTL

Zero Delay Buffer

Not Recommended for New Designs - 10/22/13

For replacement device use ICS8725BY-01LF

ICS8624

DATA SHEET

NRND

Features

•

Fully integrated PLL

Five differential HSTL output pairs

Selectable differential CLKx/nCLKx input pairs

CLKx/nCLKx pairs can accept the following differential



input levels: LVPECL, LVDS, HSTL, HCSL, SSTL

Output frequency range: 31.25MHz to 700MHz

Input frequency range: 31.25MHz to 700MHz

VCO range: 250MHz to 700MHz

External feedback for “zero delay” clock regeneration

Cycle-to-cycle jitter: 25ps (maximum)

Output skew: 25ps (maximum)

Static phase offset: ±100ps

3.3V core, 1.8V output operating supply

0°C to 70°C ambient operating temperature

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

General Description

The ICS8624 is a high performance, 1-to-5

Differential-to-HSTL zero delay buffer and a member

HiPerClockS™

of the HiPerClockS™ family of High Performance

Clock Solutions from IDT. The ICS8624 has two

selectable clock input pairs. The CLK0, nCLK0 and

CLK1, nCLK1 pair can accept most standard differential input levels.

The VCO operates at a frequency range of 250MHz to 700MHz.

Utilizing one of the outputs as feedback to the PLL, output

frequencies up to 700MHz can be regenerated with zero delay with

respect to the input. Dual reference clock inputs support redundant

clock or multiple reference applications.

ICS

Block Diagram

nQ0

PLL_SEL

nQ1

Pin Assignment

PLL_SEL

GND

DDA

DDO

nQ4

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

FB_IN

nFB_IN

÷4, ÷8

32 31 30 29 28 27 26 25

SEL0

SEL1

nQ2

nQ3

10 11 12 13 14 15 16

nFB_IN

FB_IN

DDO

GND

nQ0

DDO

nQ3

nQ2

nQ1

DDO

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

PLL

nQ4

SEL0

SEL1

ICS8624

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

ICS8624BY REVISION F OCTOBER 22, 2013

ICS8624 Data Sheet

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Table 1. Pin Descriptions

Number

1, 2

Name

SEL0, SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

Input

Type

Pulldown

Pullup

Pulldown

Pullup

Pulldown

Description

Determines the input and output frequency range noted in Table 3A.



LVCMOS / LVTTL interface levels.

Non-inverting differential clock input.

Inverting differential clock input.

Non-inverting differential clock input.

Inverting differential clock input.

Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0,

nCLK0. LVCMOS/LVTTL interface levels.

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset

causing the true outputs Qx to go low and the inverted outputs nQx to go high.

When logic LOW, the internal dividers and the outputs are enabled.



LVCMOS / LVTTL interface levels.

Core supply pins.

Pullup

Pulldown

Inverting differential feedback input to phase detector for regenerating clocks with

“Zero Delay.”

Non-inverted differential feedback input to phase detector for regenerating clocks

with “Zero Delay.”

Power supply ground.

Differential output pair. HSTL interface levels.

Output supply pins.

Differential output pair. HSTL interface levels.

Analog supply pin.

Pullup

PLL select. Selects between the PLL and reference clock as the input to the

dividers. When LOW, selects reference clock. When HIGH, selects PLL.

LVCMOS/LVTTL interface levels.

Input

Pulldown

9, 32

12, 13,

28, 29

14, 15

16, 17,

24, 25

18, 19

20, 21

22, 23

26, 27

nFB_IN

FB_IN

GND

nQ0, Q0

DDO

nQ1, Q1

nQ2, Q2

nQ3, Q3

nQ4, Q4

DDA

PLL_SEL

Power

Input

Power

Output

Power

Output

Power

Input

NOTE:

Pullup and Pulldown

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLUP

PULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

Maximum

Units



ICS8624BY REVISION F OCTOBER 22, 2013

ICS8624 Data Sheet

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Function Tables

Table 3A. Control Input Function Table

Inputs

Outputs

PLL_SEL = 1

PLL Enable Mode

Q[0:4], nQ[0:4]

÷1

SEL1

SEL0

Reference Frequency Range (MHz)*

250 - 700

125 - 350

62.5 - 175

31.25 - 87.5

*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.

Table 3B. PLL Bypass Function Table

Inputs

Outputs

PLL_SEL = 0

PLL Bypass Mode

SEL0

Q[0:4], nQ[0:4]

÷4

÷8

SEL1

ICS8624BY REVISION F OCTOBER 22, 2013

ICS8624 Data Sheet

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device.



These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond



those listed in the

DC Characteristics or AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for



extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

Outputs, V

Package Thermal Impedance,



Storage Temperature, T

STG

Rating

4.6V

-0.5V to V

+ 0.5V

-0.5V to V

DDO

+ 0.5V

47.9C/W (0 lfpm)

-65C to 150C

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics,

= 3.3V ± 5%, V

DDO

= 1.5V to 2V, T

= 0°C to 70°C

Symbol

DDA

DDO

DDA

DDO

Parameter

Core Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

Test Conditions

Minimum

3.135

1.5

Typical

3.3

1.8

Maximum

3.465

2.0

120

Units

Table 4B. LVCMOS/LVTTL DC Characteristics,

= 3.3V ± 5%, V

DDO

= 1.8V ± 0.2V, T

= 0°C to 70°C

Symbol

Parameter

Input High Voltage

Input Low Voltage

CLK_SEL,

SEL[0:1], MR

PLL_SEL

CLK_SEL,

SEL[0:1], MR

PLL_SEL

= V

= 3.465V

= V

= 3.465V

= 3.465V, V

= 0V

= 3.465V, V

= 0V

-5

-150

Test Conditions

Minimum

-0.3

Typical

Maximum

+ 0.3

0.8

150

Units

µA

Input High Current

Input Low Current

ICS8624BY REVISION F OCTOBER 22, 2013

ICS8624 Data Sheet

LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Table 4C. Differential DC Characteristics,

= 3.3V ± 5%, V

DDO

= 1.8V ± 0.2V, T

= 0°C to 70°C

Symbol

Parameter

FB_IN, CLK0, CLK1

Input High Current

nFB_IN, nCLK0, nCLK1

FB_IN, CLK0, CLK1

CMR

Input Low Current

nFB_IN, nCLK0, nCLK1

Peak-to-Peak Voltage; NOTE 1

Common Mode Input Voltage; NOTE 1, 2

Test Conditions

= V

= 3.465V

= V

= 3.465V

= 3.465V, V

= 0V

= 3.465V, V

= 0V

-5

-150

0.1

0.5

1.3

– 0.85

Minimum

Typical

Maximum

150

Units

µA

NOTE 1: V

should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as V

Table 4D. HSTL DC Characteristics,

= 3.3V ± 5%, V

DDO

= 1.8V ± 0.2V, T

= 0°C to 70°C

Symbol

SWING

Parameter

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Output Crossover Voltage; NOTE 2

Peak-to-Peak Output Voltage Swing

Test Conditions

Minimum

1.0

0.6

Typical

Maximum

1.4

0.4

1.1

Units

NOTE 1: Outputs terminated with 50 to ground.

NOTE 2: Defined with respect to output voltage swing at a given condition.

Table 5. Input Frequency Characteristics,

= 3.3V ± 5%, V

DDO

= 1.8V ± 0.2V, T

= 0°C to 70°C

Symbol

Parameter

Input Frequency

CLK0, nCLK0,

CLK1, nCLK1

Test Conditions

PLL_SEL = 1

PLL_SEL = 0

Minimum

31.25

Typical

Maximum

700

Units

MHz

ICS8624BY REVISION F OCTOBER 22, 2013

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8624BYLFT Related Products

	8624BYLFT	8624BYLF	8624BY	8624BYT
Description	TQFP-32, Reel	TQFP-32, Tray	PLL Based Clock Driver, 8624 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32	PLL Based Clock Driver, 8624 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
Is it lead-free?	Lead free	Lead free	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP	QFP	QFP
package instruction	LQFP, QFP32,.35SQ,32	LQFP, QFP32,.35SQ,32	LQFP, QFP32,.35SQ,32	LQFP, QFP32,.35SQ,32
Contacts	32	32	32	32
Reach Compliance Code	compliant	compliant	not_compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
series	8624	8624	8624	8624
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G32	S-PQFP-G32	S-PQFP-G32	S-PQFP-G32
JESD-609 code	e3	e3	e0	e0
length	7 mm	7 mm	7 mm	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3	3	3
Number of functions	1	1	1	1
Number of terminals	32	32	32	32
Actual output times	5	5	5	5
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32	QFP32,.35SQ,32	QFP32,.35SQ,32	QFP32,.35SQ,32
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	260	260	240	240
power supply	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V	1.8,3.3 V
Prop。Delay @ Nom-Sup	4.4 ns	4.4 ns	4.4 ns	4.4 ns
propagation delay (tpd)	4.4 ns	4.4 ns	4.4 ns	4.4 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.025 ns	0.025 ns	0.025 ns	0.025 ns
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	20	20
width	7 mm	7 mm	7 mm	7 mm
minfmax	31.25 MHz	31.25 MHz	31.25 MHz	31.25 MHz

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