Low Skew, 1-to-5 Differential-to-HSTL
Zero Delay Buffer
Not Recommended for New Designs - 10/22/13
For replacement device use ICS8725BY-01LF
ICS8624
DATA SHEET
NRND
Features
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Fully integrated PLL
Five differential HSTL output pairs
Selectable differential CLKx/nCLKx input pairs
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 25ps (maximum)
Static phase offset: ±100ps
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS8624 is a high performance, 1-to-5
Differential-to-HSTL zero delay buffer and a member
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS8624 has two
selectable clock input pairs. The CLK0, nCLK0 and
CLK1, nCLK1 pair can accept most standard differential input levels.
The VCO operates at a frequency range of 250MHz to 700MHz.
Utilizing one of the outputs as feedback to the PLL, output
frequencies up to 700MHz can be regenerated with zero delay with
respect to the input. Dual reference clock inputs support redundant
clock or multiple reference applications.
ICS
Block Diagram
Q0
nQ0
PLL_SEL
Q1
nQ1
Pin Assignment
PLL_SEL
GND
GND
V
DDA
V
DDO
Q4
nQ4
V
DD
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
÷4, ÷8
0
0
1
32 31 30 29 28 27 26 25
SEL0
SEL1
1
2
3
4
5
6
7
8
9
V
DD
Q2
nQ2
Q3
nQ3
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nFB_IN
FB_IN
V
DDO
GND
GND
nQ0
Q0
V
DDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
DDO
1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
PLL
Q4
nQ4
SEL0
SEL1
MR
ICS8624
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8624BY REVISION F OCTOBER 22, 2013
1
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Table 1. Pin Descriptions
Number
1, 2
3
4
5
6
7
Name
SEL0, SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Description
Determines the input and output frequency range noted in Table 3A.
LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0,
nCLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Pullup
Pulldown
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Power supply ground.
Differential output pair. HSTL interface levels.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
8
MR
Input
Pulldown
9, 32
10
11
12, 13,
28, 29
14, 15
16, 17,
24, 25
18, 19
20, 21
22, 23
26, 27
30
31
V
DD
nFB_IN
FB_IN
GND
nQ0, Q0
V
DDO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
V
DDA
PLL_SEL
Power
Input
Input
Power
Output
Power
Output
Output
Output
Output
Power
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8624BY REVISION F OCTOBER 22, 2013
2
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Q[0:4], nQ[0:4]
÷1
÷1
÷1
÷1
SEL1
0
0
1
1
SEL0
0
1
0
1
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL0
0
1
0
1
Q[0:4], nQ[0:4]
÷4
÷4
÷4
÷8
SEL1
0
0
1
1
ICS8624BY REVISION F OCTOBER 22, 2013
3
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.5V to 2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
0
Test Conditions
Minimum
3.135
3.135
1.5
Typical
3.3
3.3
1.8
Maximum
3.465
3.465
2.0
120
15
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK_SEL,
SEL[0:1], MR
PLL_SEL
CLK_SEL,
SEL[0:1], MR
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
Input High Current
I
IL
Input Low Current
ICS8624BY REVISION F OCTOBER 22, 2013
4
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
FB_IN, CLK0, CLK1
Input High Current
nFB_IN, nCLK0, nCLK1
FB_IN, CLK0, CLK1
I
IL
V
PP
V
CMR
Input Low Current
nFB_IN, nCLK0, nCLK1
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.1
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. HSTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
1.0
0
40
0.6
Typical
Maximum
1.4
0.4
60
1.1
Units
V
V
%
V
NOTE 1: Outputs terminated with 50 to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 5. Input Frequency Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 70°C
Symbol
F
IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
ICS8624BY REVISION F OCTOBER 22, 2013
5
©2013 Integrated Device Technology, Inc.
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