KT8554B/7B
1 CHIP CODECS
INTRODUCTION
The KT8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide
all the functions required to interface a full-duplex voice
telephone circuit with a time-division-multiplex (TDM)
system.
These devices are designed to perform the transmit encoding
and receive decoding as well as the transmit and receive filter-
ing functions in PCM system. They are intended to be used
at the analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog
signals prior to encoding and after decoding. These combina-
tion devices perform the encoding and decoding of voice and
call progress tones as well as the signalling and supervision
information.
16-CERDIP
16-DIP-
300A
FEATURES
•
Complete CODEC and filtering system
•
Meets or exceeds AT&T D3/D4 and CCITT
specifications
µ-Law
: KT8554B, A-Law : KT8557B
•
On-chip auto zero, sample and hold, and precision
voltage references
•
Low power dissipation : 60mW (operating)
3mW (standby)
• ±
5V operation
•
TTL or CMOS compatible
•
Automatic power down
16-SOP-BD300
-SG
ORDERING INFORMATION
Device
KT8554BJ
KT8557BJ
KT8557BN
KT8554BN
Package
16-CERDIP
16-DIP-300A
16-SOP-BD300
-SG
Operating Temperature
- 25 ~ 125°C
- 25 ~ 70°C
- 25 ~ 70°C
PIN CONFIGURATION
KT8554BD
KT8557BD
V
BB
GNDA
1
16
VF
X
I
+
VF
X
I
-
GS
X
TS
X
FS
X
S
D
X
BCLK
2
15
VF
R
O
V
CC
FS
R
D
R
BCLK
R
/CLKSEL
3
14
4
KT8554B/7B
13
5
12
6
11
7
10
X
MCLK
R
/PDN
8
9
MCLK
X
Fig. 1
KT8554B/7B
1 CHIP CODECS
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
Symbol
V
BB
GNDA
VF
R
O
V
CC
FS
R
D
R
BCLK
R
/
CLKSEL
MCLK
R
/
PDN
MCLK
X
BCLK
X
D
X
FS
X
TS
X
GS
X
VF
X
I
-
VF
X
I
+
Description
V
BB
= - 5V
±5%.
Analog ground.
Analog output of the receive power Amp.
V
CC
= +5V ± 5%.
Receive frame sync pulse. 8KHz pulse train.
PCM data input.
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master
clock in normal operation and BCLK
X
is used for both TX and RX directions.
Alternately direct clock input available, very from 64KHz to 2.048MHz.
When MCLK
R
is connected continuously high, the device is powered down.
Normally connected continusously low, MCLK
X
is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.
Must be1.536MHz/1.544MHz or 2.048MHz.
May be vary from 64KHz to 2.048MHz but BCLK
X
is externally tied with MCLK
X
in normal operation.
PCM data output.
TX frame sync pulse. 8KHz pulse train.
Changed from high to low during the encoder timeslot. Open drain output.
Analog output of the TX input amplifier.
Used to set gain through external resistor.
Inverting input stage of the TX analog signal.
Non-inverting input stage of the TX analog signal.
7
8
9
10
11
12
13
14
15
16
ABSOLUTE MAXIMUM RATINGS
(Ta = 25
o
C)
Characteristic
Positive Supply Voltage
Negative Supply Voltage
Voltage at Any Analog Input or Output
Voltage at Any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 secs)
Symbol
V
CC
V
BB
V
I (A)
V
l (D)
Ta
T
STG
T
LEAD
Value
7
-7
V
CC
+ 0.3 to V
BB
- 0.3
V
CC
+ 0.3 to GNDA - 0.3
- 25 to + 125
- 65 to + 150
300
Unit
V
V
V
V
o
o
o
C
C
C
KT8554B/7B
1 CHIP CODECS
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
±5%,
V
BB
= - 5.0V
±5%,
GNDA = 0V, Ta = 0
o
C to 70
o
C ; typical characteristics
specified at V
CC
= 5.0V, V
BB
= - 5.0V, Ta = 25
o
C ; all signals referenced to GNDA).
Characteristic
Power
Dissipation
I
CC (DOWN)
I
BB (DOWN)
I
CC (A)
I
BB (A)
V
IL
V
IH
I
IL
I
IH
V
OL
GNDA
≤
V
IN
≤V
IL
, all digital inputs
V
IH
≤
V
IN
≤
V
CC
D
X
,I
L
= 3.2mA
SIG
R
, I
L
= 1.0mA
TS
X
, I
L
= 3.2mA,open drain
D
X
, I
H
= -3.2mA
SIG
R
, I
H
= -1.0 mA
D
X
, GNDA
≤
V
O
≤
V
CC
2.4
2.4
-10
10
2.2
-10
-10
10
10
0.4
0.4
0.4
No Load
No Load
No Load
No Load
0.5
0.05
6.0
6.0
1.5
0.3
9.0
9.0
0.6
mA
mA
mA
mA
V
V
µA
µA
V
V
V
V
V
µA
Symbol
Test Conditions
Min
Typ
Max
Unit
Power-Down Current
Power-Down Current
Active Current
Active Current
Digital Interface
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output Current in High Impedance
State (TRI-STATE)
Analog Interface with Receive Filter
Output Resistance
Load Resistance
Load Capacitance
Output DC Offset Voltage
Input Leakage Current
Input Resistance
Output Resistance
Load Resistance
Load Capacitance
Output Dynamic Range
Voltage Gain
Unity Gain Bandwidth
Offset Voltage
Common-Mode Voltage
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
V
OH
I
O (HZ)
R
O
R
L
C
L
V
OO (RX)
I
LKG
R
I
R
O
R
L
C
L
V
OD (TX)
G
V
BW
V
IO (TX)
V
CM (TX)
CMRR
PSRR
Pin VF
R
O
VF
R
O =
±2.5V
600
1
3
500
Ω
Ω
pF
mV
nA
MΩ
Ω
KΩ
pF
V
V/V
-200
-2.5V≤V≤+2.5V, VF
X
I + or VF
X
I -
-2.5V≤V≤+2.5V, VF
X
I + or VF
X
I -
Closed loop, unity gain
GS
X
GS
X
GS
X
, R
L
≤10KW
VF
X
I + to GS
X
±2.8
5,000
1
-20
CMRRXA > 60dB
DC Test
DC Test
-2.5
60
60
2
10
-200
10
1
200
200
3
50
Analog Interface with Transmit input Amplifier
MHz
20
2.5
mV
V
dB
dB
KT8554B/7B
1 CHIP CODECS
TIMING CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0
±5%,
V
BB
= -5.0V
±5%,
GNDA = 0V, Ta = 0
o
C to 70
o
C; typical characteristics
specified at V
CC
= 5.0V, V
BB
= -5.0V, Ta = 25
o
C; all signals referenced to GNDA.)
Characteristic
Symbol
Test Conditions
Depends on the device used and the
BCLK
R
/CLKSEL Pin.
MCLK
X
and MCLK
R
t
PB
= 488ns
t
PB
= 488ns
Long frame only
Short frame only
Long frame only
Load = 150pF plus 2 LSTTL loads
Load = 150pF plus 2 LSTTL loads
50
0
0
80
0
180
140
165
Min
Typ
1.536
1.544
2.048
50
50
Max
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Frequency of Master Clocks
Rise Time of Bit Clock
Fall Time of Bit Clock
Holding Time from Bit Clock
Low to Frame Sync
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
Delay Time from BCLK
X
High
to Data Valid
Delay Time to TS
X
Low
Delay Time from BCLK
X
Low to
Data Output Disabled
Delay Time to Valid Data from
FS
X
or BCLK
X
, Whichever
Comes Later
Set-Up Time from D
R
Valid to
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low
to D
R
Invalid
Set-Up Time from FS
X/R
to
BCLK
X/R
Low
Width of Master Clock High
Width of Master Clock Low
Rise Time of Master Clock
Fall Time of Master Clock
Set-Up Time from BCLK
X
High
(and FS
X
In Long Frame Sync
Mode) to MCLK
X
Falling Edge
Period of Bit Clock
Width of Bit Clock High
Width of Bit Clock Low
f
MCK
t
R (BCK)
t
F (BCK)
t
H (LFS)
t
H (HFS)
t
SU (FBCL)
t
D (HDV)
t
D (TSXL)
t
D (LDD)
t
D (VD)
C
L
= 0pF to 150pF
20
165
ns
t
SU (DR BL)
t
H (BL DR)
t
SU (FBLS)
t
W (MCKH)
t
W (MCKL)
t
R (MCK)
t
F( MCK)
t
SU (BHMF)
t
CK
t
W (BCKH)
t
W (BCKL)
V
IH
= 2.2V
V
IL
= 0.6V
Short frame sync pulse (1 or 2 bit
clock periods long) (Note1)
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
First bit clock after the leading
edge of FS
X
50
50
50
160
160
50
50
ns
ns
ns
ns
ns
ns
ns
485
160
160
488
15,72
5
ns
ns
ns
KT8554B/7B
1 CHIP CODECS
TIMING CHARACTERISTICS
(Continued)
Characteristic
Hold Time from BCLK
X/R
Low
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FS
X
or FS
R
)
Minimum Width of the Frame
Sync Pulse (Low Level)
Symbol
t
H (BLFL)
Test Conditions
Short frame sync pulse (1 or 2 bit
clock periods long) (Note 1)
Long frame sync pulse (from 3 to
8 bit clock periods long)
64K bit/s operating mode
Min
100
Typ
Max
Unit
ns
t
H (3rd )
100
ns
t
WFL
160
ns
Note 1 : For short frame sync timing, FS
X
and FS
R
must go high while their respective bit clocks are high.
TIMING DIAGRAM
t
D (TS X L)
t
F (MCK)
t
R (MCK)
t
W (MCKL)
t
D (LDD)
t
CK
t
W (MCKH)
t
SU (BHMF)
t
H (HFS)
t
SU (FBLS)
t
H (BLFL)
t
D (HDV)
t
D (LDD)
t
H (HFS)
t
SU (FBCL)
t
H (BLFL)
t
SU (DR BL)
t
H (BLDR)
t
H (BLDR)
Fig. 2. Short Frame Sync Timing
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