Integrated
Circuit
Systems, Inc.
ICS2510C
3.3V Phase-Lock Loop Clock Driver
General Description
The ICS2510C
is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The
ICS2510C
operates at 3.3V VCC
and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter copies
of CLKIN. Output signal duty cycles are adjusted to 50
percent, independent of the duty cycle at CLKIN. Outputs
can be enabled or disabled via control (OE) inputs. When the
OE inputs are high, the outputs align in phase and frequency
with CLKIN; when the OE inputs are low, the outputs are
disabled to the logic low state.
The
ICS2510C
does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The test
mode shuts off the PLL and connects the input directly to the
output buffer. This test mode, the
ICS2510C
can be use as
low skew fanout clock buffer device. The
ICS2510C
comes
in 24 pin 173mil Thin Shrink Small-Outline package (TSSOP)
package.
Features
•
•
•
•
•
•
•
•
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 25MHz to 175MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
Block Diagram
FBOUT
CLK0
CLK1
CLK2
FBIN
CLKIN
PLL
CLK3
CLK4
AVCC
CLK5
CLK6
CLK7
CLK8
CLK9
OE
Pin Configuration
AGND
VCC
CLK0
CLK1
CLK2
GND
GND
CLK3
CLK4
VCC
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKIN
AVCC
VCC
CLK9
CLK8
GND
GND
CLK7
CLK6
CLK5
VCC
FBIN
24 Pin TSSOP
2510 C Rev C 11/01/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS2510C
ICS2510C
Pin Descriptions
PIN NUMBER
1
2, 10, 14
3
4
5
6, 7, 18, 19
8
9
11
12
13
15
16
17
20
21
22
23
24
PIN NAME
AGND
VCC
CLK0
CLK1
CLK2
GND
CLK3
CLK4
OE
1
FBOUT
FBIN
CLK5
CLK6
CLK7
CLK8
CLK9
VCC
AVCC
CLKIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
PWR
IN
IN
DESCRIPTION
Analog Ground
Power Supply (3.3V)
Buffered clock output.
Buffered clock output.
Buffered clock output.
Ground
Buffered clock output.
Buffered clock output.
Output enable (has internal pull_up). When high, normal operation.
When low, clock outputs are disabled to a logic low state.
Feedback output
Feedback input
Buffered clock output.
Buffered clock output.
Buffered clock output.
Buffered clock output.
Buffered clock output.
Power Supply (3.3V) digital supply.
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
Clock input
Note:
1. Weak pull-ups on these inputs
Functionality
INPUTS
OE
0
1
AVCC
3.33
3.33
CLK (9:0)
0
Driven
OUTPUTS
FBOUT
Driven
Driven
Source
PLL
PLL
CLKIN
CLKIN
PLL
Shutdown
N
N
Y
Y
0
0
1
0
Test mode:
When AVCC is 0, shuts off the PLL
and connects the input directly to the output buffers
Buffer Mode
0
Driven
Driven
Driven
2
ICS2510C
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .
AVCC < (V
cc
+ 0.7V)
4.3 V
GND –0.5 V to V
cc
+0.5 V
0°C to +70°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - OUTPUT
T
A
= 0 - 70C; V
DD
= V
DDL
= 3.3 V +/-10%; C
L
= 20 - 30 pF; RL = 470 Ohms (unless otherwise stated)
V
O
= V
DD
*(0.5)
V
O
= V
DD
*(0.5)
I
OH
= 8 mA
I
OL
= 8 mA
V
OL
= 0.8 V, V
OH
= 2.0 V
V
OH
= 2.0 V, V
OL
= 08 V
V
T
= 1.5V;Cl=30pF
V
T
= Vdd/2; Fout<66.6MHz
at 66MHz - 100MHz ; loaded Outputs
at 133MHz ; loaded Outputs
10000 cycles; Cl=30pF
V
T
= 1.5 V (Window) Output to Output
V
T
= Vdd/2; CLKIN-FBIN
V
T
= Vdd/2; CLKIN-FBIN;
Phase error -Jitter
T
pe3
Delay Jitter @ 133MHz
D
R1
V
T
= 1.5 V; PLL_EN = 0
Delay Input-Output
1
1
Guaranteed by design, not 100% tested in production.
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Rise Time
1
Fall Time
1
Duty Cycle
1
Duty Cycle
1
Cycle to Cycle jitter
1
Cycle to Cycle jitter
1
Absolute Jitter
1
Skew
1
Phase error
SYMBOL
R
DSP
R
DSN
V
OH
V
OL
T
r
T
f
D
t
D
t
Tcyc-cyc
Tcyc-cyc
Tjabs
T
sk
T
pe
CONDITIONS
MIN
TYP
36
32
2.9
0.25
1.4
1.5
50
50
52
39
57
80
40
35
3.3
MAX UNITS
Ω
Ω
50
V
0.4
V
2.1
ns
2.7
ns
60
%
55
%
100
ps
75
ps
ps
150
ps
150
ps
50
3.7
ps
ns
2.4
0.5
0.5
40
45
-150
-150
-50
3
ICS2510C
Electrical Characteristics - Input & Supply
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
Input Low Current
I
IL
V
IN
= 0 V;
C
L
= 0 pF; F
IN
@ 66M
Operating current
I
DD1
1
Input Capacitance
C
IN
Logic Inputs
1
C
O
Output Capacitance
Logic Outputs
1
MIN
2
V
SS
-0.3
TYP
0.1
19
140
4
8
MAX UNITS
V
DD
+0.3
V
0.8
V
100
uA
50
uA
170
mA
pF
pF
Guarenteed by design, not 100% tested in production.
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Symbol
Fclk
Parameter
Input clock frequency
Test Conditions
Min.
25
Max.
175
Unit
MHz
Input clock frequency
40
60
%
duty cycle
Stabilization time
After power up
1
ms
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be
Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not
4
ICS2510C
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
500
Ω
Figure 1. Load Circuit for Outputs
Notes:
Figure 2. Voltage Waveforms
1. C
L
includes probe and jig capacitance.
Propagation Delay Times
2. All input pulses are supplied by generators having the following
characteristics:
PRR
£
133 MHz, Z
O
= 5 0
W,
T
r
£
1.2 ns, T
f
£
1.2 ns.
3. The outputs are measured one at a time with one transition per measurement.
Figure 3. Phase Error and Skew Calculations
5
京公网安备 11010802033920号
EEWORLD
