XC2064-100PG68C datasheet, PDF

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XC2064-100PG68C: DescriptionField Programmable Gate Array, 64 CLBs, 600 Gates, 100MHz, 64-Cell, CMOS, CPGA68, CERAMIC, PGA-68; CategoryProgrammable logic devices Programmable logic; File Size2MB，42 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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XC2064-100PG68C Overview

Field Programmable Gate Array, 64 CLBs, 600 Gates, 100MHz, 64-Cell, CMOS, CPGA68, CERAMIC, PGA-68

XC2064-100PG68C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	PGA
package instruction	PGA, PGA68,11X11
Contacts	68
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	122 FLIP-FLOPS; TYP. GATES = 600-1000
maximum clock frequency	100 MHz
Combined latency of CLB-Max	7.5 ns
JESD-30 code	S-CPGA-P68
length	27.94 mm
Configurable number of logic blocks	64
Equivalent number of gates	600
Number of entries	58
Number of logical units	64
Output times	58
Number of terminals	68
Maximum operating temperature	85 °C
Minimum operating temperature
organize	64 CLBS, 600 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA68,11X11
Package shape	SQUARE
Package form	GRID ARRAY
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.064 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	27.94 mm

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XC2064-100PG68C Related Products

	XC2064-100PG68C	XC2018-100PC84C	XC2018-100PG84C	XC2064-50CD48I	XC2064-100PC68C	XC2018-100PC68C
Description	Field Programmable Gate Array, 64 CLBs, 600 Gates, 100MHz, 64-Cell, CMOS, CPGA68, CERAMIC, PGA-68	Field Programmable Gate Array, 100 CLBs, 1000 Gates, 100MHz, 100-Cell, CMOS, PQCC84, PLASTIC, LCC-84	Field Programmable Gate Array, 100 CLBs, 1000 Gates, 100MHz, 100-Cell, CMOS, CPGA84, CERAMIC, PGA-84	Field Programmable Gate Array, 64 CLBs, 1200 Gates, 50MHz, 64-Cell, CMOS, CDIP48, CERAMIC, DIP-48	Field Programmable Gate Array, 64 CLBs, 600 Gates, 100MHz, 64-Cell, CMOS, PQCC68, PLASTIC, LCC-68	Field Programmable Gate Array, 100 CLBs, 1000 Gates, 100MHz, 100-Cell, CMOS, PQCC68, PLASTIC, LCC-68
Is it Rohs certified?	conform to	incompatible	conform to	incompatible	incompatible	incompatible
Parts packaging code	PGA	LCC	PGA	DIP	LCC	LCC
package instruction	PGA, PGA68,11X11	QCCJ, LDCC84,1.2SQ	PGA, PGA84M,11X11	DIP, DIP48,.6	QCCJ, LDCC68,1.0SQ	QCCJ, LDCC68,1.0SQ
Contacts	68	84	84	48	68	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
Other features	122 FLIP-FLOPS; TYP. GATES = 600-1000	174 FLIP-FLOPS; TYP. GATES = 1000-1500	174 FLIP-FLOPS; TYP. GATES = 1000-1500	MAX 40 I/OS; 122 FLIP-FLOPS	122 FLIP-FLOPS; TYP. GATES = 600-1000	174 FLIP-FLOPS; TYP. GATES = 1000-1500
maximum clock frequency	100 MHz	100 MHz	100 MHz	50 MHz	100 MHz	100 MHz
Combined latency of CLB-Max	7.5 ns	7.5 ns	7.5 ns	15 ns	7.5 ns	7.5 ns
JESD-30 code	S-CPGA-P68	S-PQCC-J84	S-CPGA-P84	R-CDIP-T48	S-PQCC-J68	S-PQCC-J68
length	27.94 mm	29.3116 mm	27.94 mm	60.96 mm	24.2316 mm	24.2316 mm
Configurable number of logic blocks	64	100	100	64	64	100
Equivalent number of gates	600	1000	1000	1200	600	1000
Number of entries	58	74	74	40	58	58
Number of logical units	64	100	100	64	64	100
Output times	58	74	74	40	58	58
Number of terminals	68	84	84	48	68	68
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
organize	64 CLBS, 600 GATES	100 CLBS, 1000 GATES	100 CLBS, 1000 GATES	64 CLBS, 1200 GATES	64 CLBS, 600 GATES	100 CLBS, 1000 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	PGA	QCCJ	PGA	DIP	QCCJ	QCCJ
Encapsulate equivalent code	PGA68,11X11	LDCC84,1.2SQ	PGA84M,11X11	DIP48,.6	LDCC68,1.0SQ	LDCC68,1.0SQ
Package shape	SQUARE	SQUARE	SQUARE	RECTANGULAR	SQUARE	SQUARE
Package form	GRID ARRAY	CHIP CARRIER	GRID ARRAY	IN-LINE	CHIP CARRIER	CHIP CARRIER
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.064 mm	5.08 mm	4.318 mm	9.271 mm	4.445 mm	4.445 mm
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.5 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.5 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	NO	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	INDUSTRIAL	OTHER	OTHER
Terminal form	PIN/PEG	J BEND	PIN/PEG	THROUGH-HOLE	J BEND	J BEND
Terminal pitch	2.54 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	QUAD	PERPENDICULAR	DUAL	QUAD	QUAD
width	27.94 mm	29.3116 mm	27.94 mm	15.24 mm	24.2316 mm	24.2316 mm
JESD-609 code	-	e0	-	e0	e0	e0
Humidity sensitivity level	-	3	-	1	1	1
Terminal surface	-	TIN LEAD	-	TIN LEAD	TIN LEAD	TIN LEAD

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