INTEGRATED CIRCUITS
DATA SHEET
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•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4052B
MSI
Dual 4-channel analogue
multiplexer/demultiplexer
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Dual 4-channel analogue multiplexer/demultiplexer
DESCRIPTION
The HEF4052B is a dual 4-channel
analogue multiplexer/demultiplexer
with common channel select logic.
Each multiplexer/demultiplexer has
four independent inputs/outputs
(Y
0
to Y
3
) and a common input/output
(Z). The common channel select logic
includes two address inputs (A
0
and
A
1
) and an active LOW enable input
(E).
Both multiplexers/demultiplexers
contain four bidirectional analogue
switches, each with one side
connected to an independent
input/output (Y
0
to Y
3
) and the other
side connected to a common
input/output (Z).
With E LOW, one of the four switches
is selected (low impedance ON-state)
by A
0
and A
1
. With E HIGH, all
switches are in the high impedance
OFF-state, independent of A
0
and A
1
.
HEF4052B
MSI
V
DD
and V
SS
are the supply voltage
connections for the digital control
inputs (A
0
, A
1
and E). The V
DD
to
V
SS
range is 3 to 15 V. The analogue
inputs/outputs (Y
0
to Y
3
, and Z) can
swing between V
DD
as a positive limit
and V
EE
as a negative limit.
V
DD
−
V
EE
may not exceed 15 V.
For operation as a digital
multiplexer/demultiplexer, V
EE
is
connected to V
SS
(typically ground).
PINNING
Y
0A
to Y
3A
Y
0B
to Y
3B
A
0
, A
1
E
Z
A
, Z
B
independent inputs/outputs
independent inputs/outputs
address inputs
enable input (active LOW)
common inputs/outputs
FAMILY DATA,
I
DD
LIMITS category MSI
See Family Specifications
Fig.2 Pinning diagram.
HEF4052BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4052BD(F): 16-lead DIL; ceramic
(cerdip)
(SOT74)
HEF4052BT(D): 16-lead SO; plastic
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
January 1995
2
Philips Semiconductors
Product specification
Dual 4-channel analogue multiplexer/demultiplexer
HEF4052B
MSI
Fig.3 Schematic diagram (one switch).
FUNCTION TABLE
INPUTS
E
L
L
L
L
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (with reference to V
DD
)
Note
1. To avoid drawing V
DD
current out of terminal Z, when switch current flows into terminals Y, the voltage drop across
the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no V
DD
current will flow out
of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may
not exceed V
DD
or V
EE
.
V
EE
−18
to
+
0,5 V
A
1
L
L
H
H
X
A
0
L
H
L
H
X
CHANNEL
ON
Y
0A
−Z
A
; Y
0B
−Z
B
Y
1A
−Z
A
; Y
1B
−Z
B
Y
2A
−Z
A
; Y
2B
−Z
B
Y
3A
−Z
A
; Y
3B
−Z
B
none
January 1995
3
stm32/stm8
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