Low Skew, 1-to-5, Differential-to-3.3V
LVPECL/ECL Fanout Buffer
8735BI-01
DATA SHEET
General Description
The 8735BI-01 is a highly versatile 1:5 Differential- to-3.3V LVPECL
clock generator. The 8735BI-01 has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is
routed around the PLL and into the internal output dividers.
Features
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Five differential 3.3V LVPECL output pairs
Selectable differential input pairs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Static phase offset: 200ps (maximum)
Cycle-to-cycle jitter: 50ps (maximum)
Output skew: 55ps (maximum)
3.3V output operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
Q0
PLL_SEL
Pullup
nQ0
Q1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
0
1
1
0
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
8:1,
4:1, 2:1, 1:1,
1:2, 1:4, 1:
8
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
CLK_SEL
Pulldown
FB_IN
Pulldown
nFB_IN
Pullup
PLL
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
8735BI-01 REVISION 1 04/02/15
1
©2015 Integrated Device Technology, Inc.
8735BI-01 DATA SHEET
Pin Assignments
PLL_SEL
PLL_SEL
SEL3
SEL3
V
CCO
V
CCA
V
CCO
25
24
23
22
V
CCA
nQ4
V
CC
V
EE
Q4
32
31
30
29
28
27
26
25
24
23
22
32
31
30
29
28
27
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
nQ4
26
V
CC
V
EE
Q4
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
8735BI-01
21
20
19
18
17
8735BI-01
21
20
19
18
17
nFB_IN
FB_IN
V
EE
SEL2
SEL2
nFB_IN
FB_IN
V
CCO
V
CC
nQ0
32-pin, 7mm x 7mm LQFP Package
32-pin, 5mm x 5mm VFQFN Package
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
Name
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Description
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
Core supply pins.
Pullup
Pulldown
Pulldown
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Negative power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
2
REVISION 1 04/02/15
8
MR
Input
Pulldown
9
10
11
12
13
14
15
16
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQ0
Q0
V
CCO
Power
Input
Input
Input
Power
Output
Output
Power
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
V
CCO
V
CC
V
EE
nQ0
Q0
Q0
8735BI-01 Data Sheet
Number
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
V
CCO
nQ1
Q1
nQ2
Q2
nQ3
Q3
V
CCO
V
CCO
nQ4
Q4
V
EE
SEL3
V
CCA
PLL_SEL
V
CC
Power
Output
Output
Output
Output
Output
Output
Power
Power
Output
Output
Power
Input
Power
Input
Power
Type
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative power supply pins.
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Core supply pins.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
REVISION 1 04/02/15
3
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 DATA SHEET
Function Tables
Table 3A. Control Input Function Table
Inputs
Reference Frequency Range
(MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
Outputs
PLL_SEL = 1;
PLL Enable Mode;
Q[0:4], nQ[0:4]
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0;
PLL Bypass Mode;
Q[0:4], nQ[0:4]
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
4
REVISION 1 04/02/15
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
8735BI-01 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Junction Temperature, T
J
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
125C
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
17
Units
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
SEL[3:0], MR,
CLK_SEL
PLL_SEL
Input Low
Current
SEL[3:0], MR,
CLK_SEL
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
REVISION 1 04/02/15
5
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-3.3V LVPECL/ECL
FANOUT BUFFER
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