White Electronic Designs
512Kx8 MONOLITHIC SRAM
FEATURES
Access Times 15, 17, 20ns
Revolutionary, Center Power/Ground Pinout JEDEC
Approved
• 36 lead Ceramic SOJ (Package 100)
• 36 lead Ceramic Flat Pack (Package 226)
Evolutionary, Corner Power/Ground Pinout JEDEC
Approved
• 32 pin Ceramic DIP (Package 300)
• 32 lead Ceramic SOJ (Package 101)
• 32 lead Ceramic Thinpack™ Flat Pack
(Package 321)
32 pin, Rectangular Ceramic Leadless Chip Carrier
(Package 601)
Low Power CMOS
WMS512K8V-XXX
Low Voltage Operation
• 3.3V ± 10% Power Supply
Commercial, Industrial and Military Temperature
Range
TTL Compatible Inputs and Outputs
Fully Static Operation:
• No clock or refresh required
Three State Output
* This product is subject to change without notice.
REVOLUTIONARY PINOUT
36 FLAT PACK
36 CSOJ
TOP VIEW
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
V
CC
V
SS
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
EVOLUTIONARY PINOUT
32 DIP
32 CSOJ (DE)
32 FLAT PACK (FF)
TOP VIEW
32 CLCC
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
A12
A14
A16
A18
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
V
CC
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
V
SS
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
I/O1
I/O2
I/O3
PIN DESCRIPTION
A0-18
I/O 0-7
CS#
OE#
WE#
V
CC
V
SS
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
Power Supply
Ground
October 2004
Rev. 8
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
I/O5
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
V
SS
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Range to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
4.6
150
4.6
Unit
°C
°C
V
°C
V
CS#
H
L
L
L
OE#
X
L
X
H
WE#
X
H
L
H
WMS512K8V-XXX
TRUTH TABLE
MODE
Standby
Read
Write
Out Disable
DATA I/O
High Z
Data Out
Data In
High Z
POWER
Standby
Active
Active
Acvive
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil)
Symbol
V
CC
V
IH
V
IL
T
A
Min
3.0
2.2
-0.3
-55
Max
3.6
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Parameter
Input capacitance
Output capacitance
CAPACITANCE
T
A
= +25°C
Symbol
C
IN
C
OUT
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
OUT
= 0 V, f = 1.0 MHz
Max
12
12
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS - CMOS COMPATIBLE
V
CC
= 5.0V, GND = 0V, -55°C
≤T
A
≤
125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC
I
SS
V
OL
V
OH
Conditions
V
CC
= 3.6, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 3.6
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 3.6
I
OL
= 4.0mA
I
OH
= -4.0mA
Min
Max
10
10
100
50
0.4
Unit
μA
μA
mA
mA
V
V
2.4
October 2004
Rev. 8
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
< 125°C
Parameter Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ1
t
OLZ1
t
CHZ1
t
OHZ1
-15
Min
15
0
15
8
1
0
8
8
1
0
8
8
Max
15
0
17
8
Min
17
-17
Max
17
WMS512K8V-XXX
-20
Min
20
0
20
10
1
0
10
10
Max
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
125°C
Parameter Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW1
t
WHZ1
t
DH
-15
Min
15
12
12
9
12
0
0
2
0
Max
Min
17
12
12
9
14
0
0
3
0
-17
Max
Min
20
14
14
10
14
0
0
3
0
-20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
9
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
V
Z
≈
1.5V
(Bipolar Supply)
I
OL
Current Source
Typ
V
IL
= 0, V
IH
= 2.5
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pF
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
October 2004
Rev. 8
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
TIMING WAVEFORM - READ CYCLE
WMS512K8V-XXX
t
RC
ADDRESS
t
AA
t
RC
ADDRESS
CS#
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
ACS
t
CLZ
OE#
t
OE
t
CHZ
t
OHZ
DATA VALID
READ CYCLE 1 (CS# = OE# = V
IL
, WE# = V
IH
)
t
OLZ
DATA I/O
HIGH IMPEDANCE
READ CYCLE 2 (WE# = V
IH
)
WRITE CYCLE - WE# CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS#
t
AH
t
AS
WE#
t
WP
t
OW
t
WHZ
t
DW
DATA VALID
t
DH
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
t
WC
ADDRESS
t
AW
t
AS
CS#
t
CW
t
AH
t
WP
WE#
t
DW
t
DH
DATA I/O
WRITE CYCLE 2, CS# CONTROLLED
DATA VALID
October 2004
Rev. 8
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PACKAGE 100: 36 LEAD, CERAMIC SOJ
23.37 (0.920)
±
0.25 (0.010)
0.2 (0.008)
±
0.05 (0.002)
WMS512K8V-XXX
4.7 (0.184) MAX
0.89 (0.035)
Radius TYP
11.23 (0.442)
±
0.30 (0.012)
9.55 (0.376)
±
0.25 (0.010)
1.27 (0.050)
±
0.25 (0.01
PIN 1
IDENTIFIER
1.27 (0.050) TYP
21.6 (0.850) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 101: 32 LEAD, CERAMIC SOJ
21.1 (0.830) ± 0.25 (0.010)
0.2 (0.008)
± 0.05 (0.002)
3.96 (0.156) MAX
0.89 (0.035)
Radius TYP
11.23 (0.442)
± 0.30 (0.012)
9.55 (0.376) ± 0.25 (0.010)
1.27 (0.050) ± 0.25 (0.010)
PIN 1
IDENTIFIER
1.27 (0.050) TYP
19.1 (0.750) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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