IDT72V261LA20TFG datasheet, PDF

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IDT72V261LA20TFG: DescriptionFIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64, SLIM, GREEN, TQFP-64; Categorystorage storage; File Size301KB，27 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT72V261LA20TFG Overview

FIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64, SLIM, GREEN, TQFP-64

IDT72V261LA20TFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LFQFP, QFP64,.47SQ,20
Contacts	64
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	12 ns
Other features	RETRANSMIT
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
memory density	147456 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.02 A
Maximum slew rate	0.055 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm

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3.3 VOLT CMOS SuperSync FIFO™

16,384 x 9

32,768 x 9

•

IDT72V261LA

IDT72V271LA

FEATURES:

Choose among the following memory organizations:

IDT72V261LA

—

16,384 x 9

IDT72V271LA

—

32,768 x 9

Pin-compatible with the IDT72V281/72V291 and IDT72V2101/

72V2111SuperSync FIFOs

Functionally compatible with the 5 Volt IDT72261/72271 family

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

5V input tolerant

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

•

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write clocks (permit reading and writing

simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

DESCRIPTION:

The IDT72V261LA/72V271LA are functionally compatible versions of

the IDT72261/72271 designed to run off a 3.3V supply for very low power

consumption. The IDT72V261LA/72V271LA are exceptionally deep, high

speed, CMOS First-In-First-Out (FIFO) memories with clocked read and

FUNCTIONAL BLOCK DIAGRAM

WEN

-D

WCLK

LD SEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

WRITE CONTROL

LOGIC

RAM ARRAY

16,384 x 9

32,768 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

-Q

4673 drw 01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OCTOBER 2005

DSC-4673/3



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