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70V27L35BFGI

Description
Dual-Port SRAM, 32KX16, 35ns, CMOS, PBGA144, 12 X 12 MM, 1.40 MM HEIGHT, GREEN, FBGA-144
Categorystorage    storage   
File Size179KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

70V27L35BFGI Overview

Dual-Port SRAM, 32KX16, 35ns, CMOS, PBGA144, 12 X 12 MM, 1.40 MM HEIGHT, GREEN, FBGA-144

70V27L35BFGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeBGA
package instructionBGA,
Contacts144
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
JESD-30 codeS-PBGA-B144
JESD-609 codee3
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Number of functions1
Number of terminals144
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX16
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formBALL
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
Features:
IDT70V27S/L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/35ns (max.)
Low-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for bus
matching capability
Dual chip enables allow for depth expansion without
external logic
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP), and 144-
pin Fine Pitch BGA (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/W
R
UB
R
CE
0R
CE
1L
OE
L
LB
L
CE
1R
OE
R
LB
R
I/O
8-15L
I/O
0-7L
BUSY
L
(1,2)
I/O
8-15R
I/O
Control
I/O
Control
I/O
0-7R
BUSY
R
(1,2)
,
A
14L
A
0L
Address
Decoder
A
14L
A
0L
CE
0L
32Kx16
MEMORY
ARRAY
70V27
Address
Decoder
A
14R
A
0R
CE
1L
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
14R
A
0R
CE
0R
CE
1R
OE
R
R/
W
L
SEM
L
INT
L
(2)
(2)
R/
W
R
SEM
R
(2)
INT
R
3603 drw 01
M/
S
NOTES:
1)
BUSY
is an input as a Slave (M/S=V
IL
) and an output as a Master (M/S=V
IH
).
2)
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2008
6.01
1
©2008 Integrated Device Technology, Inc.
DSC 3603/11
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