CY7B994V-2AXI datasheet, PDF - EEWORLD Datasheet

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CY7B994V-2AXI: DescriptionPLL Based Clock Driver, 7B Series, 16 True Output(s), 0 Inverted Output(s), PQFP100, TQFP-100; Categorylogic logic; File Size412KB，23 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY7B994V-2AXI Overview

PLL Based Clock Driver, 7B Series, 16 True Output(s), 0 Inverted Output(s), PQFP100, TQFP-100

CY7B994V-2AXI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	1 week
Other features	CONFIGURABLE AS SINGLE ENDED TTL ALSO
series	7B
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.002 A
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	100
Actual output times	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	0.25 ns
propagation delay (tpd)	0.25 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.8 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
minfmax	200 MHz

CY7B994V-2AXI Preview

CY7B993V/CY7B994V

RoboClock

High-Speed Multi-Phase PLL Clock Buffer

Features

■

Functional Description

The CY7B993V and CY7B994V High-speed Multi-phase PLL

Clock Buffers offer user selectable control over system clock

functions. This multiple output clock driver provides the system

integrator with functions necessary to optimize the timing of

high-performance computer and communication systems.

These devices feature a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

Eighteen configurable outputs each drive terminated

transmission lines with impedances as low as 50 while delivering

minimal and specified output skews at LVTTL levels. The outputs are

arranged in five banks. Banks 1 to 4 of four outputs allow a divide

function of 1 to 12, while simultaneously allowing phase

adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One

of the output banks also includes an independent clock invert

function. The feedback bank consists of two outputs, which

allows divide-by functionality from 1 to 12 and limited phase

adjustments. Any one of these eighteen outputs can be

connected to the feedback input as well as driving other inputs.

Selectable reference input is a fault tolerance feature that allows

smooth change-over to secondary clock source, when the

primary clock source is not in operation. The reference inputs

and feedback inputs are configurable to accommodate both

LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

For a complete list of related documentation,

click here.

500 ps Max Total Timing Budget (TTB™) window

12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz

(CY7B994V) Input/Output Operation

Matched Pair Output Skew < 200 ps

Zero Input-to-Output Delay

18 LVTTL Outputs Driving 50 Terminated Lines

16 Outputs at 200 MHz: Commercial Temperature

6 Outputs at 200 MHz: Industrial Temperature

3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable

Reference Inputs

Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns

Multiply/Divide Ratios of 1–6, 8, 10, 12

Individual Output Bank Disable

Output High Impedance Option for Testing Purposes

Fully Integrated Phase Locked Loop (PLL) with Lock Indicator

<50-ps Typical Cycle-to-Cycle Jitter

Single 3.3V ± 10% Supply

100-pin TQFP Package

100-pin BGA Package

Cypress Semiconductor Corporation

Document Number: 38-07127 Rev. *O

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 27, 2017

CY7B993V/CY7B994V

RoboClock

Logic Block Diagram

FBKA+

FBKA–

FBKB+

FBKB–

FBSEL

REFA+

REFA–

REFB+

REFB–

REFSEL

FBF0

FBDS0

FBDS1

FBDIS

4F0

4F1

4DS0

4DS1

DIS4

3F0

3F1

3DS0

3DS1

DIS3

INV3

2F0

2F1

2DS0

2DS1

DIS2

1F0

1F1

1DS0

1DS1

DIS1

LOCK

Phase

Freq.

Detector

Filter

VCO

Control Logic

Divide and Phase

Generator

OUTPUT_MODE

Divide and

Phase

Select

Matrix

Divide and

Phase

Select

Matrix

Feedback Bank

QFA0

QFA1

Bank 4

4QA0

4QA1

4QB0

4QB1

3QA0

3QA1

3QB0

3QB1

2QA0

2QA1

2QB0

2QB1

1QA0

1QA1

1QB0

1QB1

Bank 3

Divide and

Phase

Select

Matrix

Bank 2

Divide and

Phase

Select

Matrix

Bank 1

Divide and

Phase

Select

Matrix

Document Number: 38-07127 Rev. *O

Page 2 of 23

CY7B993V/CY7B994V

RoboClock

Contents

Pinouts .............................................................................. 4

Pin Definition .................................................................... 6

Block Diagram Description .............................................. 7

Phase Frequency Detector and Filter .......................... 7

VCO, Control Logic, Divider,

and Phase Generator ......................................................... 7

Time Unit Definition ..................................................... 7

Divide and Phase Select Matrix .................................. 8

Output Disable Description .......................................... 9

INV3 Pin Function ..................................................... 10

Lock Detect Output Description ................................. 10

Factory Test Mode Description ................................. 10

Safe Operating Zone ................................................. 10

Absolute Maximum Conditions ..................................... 11

Operating Range ............................................................. 11

Electrical Characteristics ............................................... 11

Thermal Resistance ........................................................ 13

AC Test Loads and Waveforms ..................................... 13

Switching Characteristics .............................................. 14

AC Timing Diagrams ...................................................... 16

Ordering Information ...................................................... 17

Ordering Code Definitions ......................................... 17

Package Diagrams .......................................................... 18

Acronyms ........................................................................ 20

Document Conventions ................................................. 20

Units of Measure ....................................................... 20

Document History Page ................................................. 21

Sales, Solutions, and Legal Information ...................... 23

Worldwide Sales and Design Support ....................... 23

Products .................................................................... 23

PSoC®Solutions ....................................................... 23

Cypress Developer Community ................................. 23

Technical Support ..................................................... 23

Document Number: 38-07127 Rev. *O

Page 3 of 23

CY7B993V/CY7B994V

RoboClock

Pinouts

Figure 1. 100-pin TQFP pinout

FBDS1

FBDS0

FBKB+

FBKA+

FBKB–

FBSEL

FBKA–

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

GND

3F1

4F1

3F0

4F0

4DS1

3DS1

GND

4QB1

VCCN

4QB0

GND

4QA1

VCCN

4QA0

GND

2DS1

1DS1

VCCQ

4DS0

3DS0

2DS0

1DS0

GND

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

VCCQ

REFA+

REFA –

REFSEL

REFB–

REFB+

2F0

GND

2QA0

VCCN

2QA1

GND

2QB0

VCCN

2QB1

GND

FBF0

1F0

GND

VCCQ

FBDIS

DIS4

DIS3

CY7B993/4V

GND

VCCN

OUTPUT_MODE

VCCQ

Document Number: 38-07127 Rev. *O

VCCQ

3QA0

3QA1

3QB0

3QB1

GND

2F1

1F1

INV3

DIS1

DIS2

VCCQ

VCCN

LOCK

QFA0

QFA1

1QB1

1QB0

1QA1

1QA0

GND

Page 4 of 23

CY7B993V/CY7B994V

RoboClock

Pinouts

(continued)

Figure 2. 100-pin BGA pinout

1QB1

1QB0

1QA1

1QA0

QFA0

QFA1

FBKB+

VCCQ

FBKA–

FBKA+

VCCN

VCCQ

FBKB–

FBSEL

REFA+

GND

VCCQ

GND

REFA–

LOCK

4F0

3F1

(3_level) (3_level)

4DS1

(3_level)

3DS1

(3_level)

GND

FBDS1 FBDS0

2F0

(3_level) (3_level) (3_level)

3F0

4F1

(3_level) (3_level)

VCCQ

REFSEL REFB–

4QB1

VCCN

GND

(3_level)

FBF0

(3_level)

VCCN

REFB+

4QB0

VCCN

GND

VCCN

2QA0

4QA1

2DS1

(3_level)

VCCQ

GND

VCCQ

1F0

(3_level)

2QA1

4QA0

1DS1

1DS0

(3_level) (3_level)

VCCQ

GND

VCCQ

OUTPUT

MODE FBDIS

(3_level)

INV3

(3_level)

DIS3

2QB0

4DS0

3DS0

2DS0

(3_level) (3_level) (3_level)

2F1

1F1

(3_level) (3_level)

DIS1

VCCN

GND

2QB1

DIS2

VCCN

3QA0

3QA1

GND

3QB0

3QB1

DIS4

Document Number: 38-07127 Rev. *O

Page 5 of 23

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CY7B994V-2AXI Related Products

	CY7B994V-2AXI	CY7B994V-2BBI
Description	PLL Based Clock Driver, 7B Series, 16 True Output(s), 0 Inverted Output(s), PQFP100, TQFP-100	PLL Based Clock Driver, 7B Series, 16 True Output(s), 0 Inverted Output(s), PBGA100, BGA-100
Is it lead-free?	Lead free	Contains lead
Is it Rohs certified?	conform to	incompatible
Maker	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	QFP	BGA
package instruction	TQFP-100	BGA-100
Contacts	100	100
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Other features	CONFIGURABLE AS SINGLE ENDED TTL ALSO	CONFIGURABLE AS SINGLE ENDED TTL ALSO
series	7B	7B
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	S-PQFP-G100	S-PBGA-B100
JESD-609 code	e3	e0
length	14 mm	11 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.002 A	0.03 A
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	100	100
Actual output times	16	16
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LBGA
Encapsulate equivalent code	QFP100,.63SQ,20	BGA100,10X10,40
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260	220
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	0.25 ns	0.5 ns
propagation delay (tpd)	0.25 ns	0.25 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.8 ns	0.8 ns
Maximum seat height	1.6 mm	1.4 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V
Minimum supply voltage (Vsup)	2.97 V	2.97 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	BALL
Terminal pitch	0.5 mm	1 mm
Terminal location	QUAD	BOTTOM
Maximum time at peak reflow temperature	30	NOT SPECIFIED
width	14 mm	11 mm
minfmax	200 MHz	200 MHz

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