CY7B993V/CY7B994V
RoboClock
®
High-Speed Multi-Phase PLL Clock Buffer
High-Speed Multi-Phase PLL Clock Buffer
Features
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Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated
transmission lines with impedances as low as 50 while delivering
minimal and specified output skews at LVTTL levels. The outputs are
arranged in five banks. Banks 1 to 4 of four outputs allow a divide
function of 1 to 12, while simultaneously allowing phase
adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One
of the output banks also includes an independent clock invert
function. The feedback bank consists of two outputs, which
allows divide-by functionality from 1 to 12 and limited phase
adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change-over to secondary clock source, when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
For a complete list of related documentation,
click here.
500 ps Max Total Timing Budget (TTB™) window
12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz
(CY7B994V) Input/Output Operation
Matched Pair Output Skew < 200 ps
Zero Input-to-Output Delay
18 LVTTL Outputs Driving 50 Terminated Lines
16 Outputs at 200 MHz: Commercial Temperature
6 Outputs at 200 MHz: Industrial Temperature
3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable
Reference Inputs
Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
Multiply/Divide Ratios of 1–6, 8, 10, 12
Individual Output Bank Disable
Output High Impedance Option for Testing Purposes
Fully Integrated Phase Locked Loop (PLL) with Lock Indicator
<50-ps Typical Cycle-to-Cycle Jitter
Single 3.3V ± 10% Supply
100-pin TQFP Package
100-pin BGA Package
Cypress Semiconductor Corporation
Document Number: 38-07127 Rev. *O
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 27, 2017
CY7B993V/CY7B994V
RoboClock
®
Logic Block Diagram
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
FBF0
FBDS0
FBDS1
FBDIS
4F0
4F1
4DS0
4DS1
DIS4
3F0
3F1
3DS0
3DS1
DIS3
INV3
2F0
2F1
2DS0
2DS1
DIS2
1F0
1F1
1DS0
1DS1
DIS1
LOCK
Phase
Freq.
Detector
Filter
VCO
Control Logic
Divide and Phase
Generator
FS
OUTPUT_MODE
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
3
3
Feedback Bank
3
3
3
3
3
3
3
QFA0
QFA1
Bank 4
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
Bank 3
3
3
3
3
3
3
3
3
3
Divide and
Phase
Select
Matrix
Bank 2
Divide and
Phase
Select
Matrix
Bank 1
3
3
3
3
Divide and
Phase
Select
Matrix
Document Number: 38-07127 Rev. *O
Page 2 of 23
CY7B993V/CY7B994V
RoboClock
®
Contents
Pinouts .............................................................................. 4
Pin Definition .................................................................... 6
Block Diagram Description .............................................. 7
Phase Frequency Detector and Filter .......................... 7
VCO, Control Logic, Divider,
and Phase Generator ......................................................... 7
Time Unit Definition ..................................................... 7
Divide and Phase Select Matrix .................................. 8
Output Disable Description .......................................... 9
INV3 Pin Function ..................................................... 10
Lock Detect Output Description ................................. 10
Factory Test Mode Description ................................. 10
Safe Operating Zone ................................................. 10
Absolute Maximum Conditions ..................................... 11
Operating Range ............................................................. 11
Electrical Characteristics ............................................... 11
Thermal Resistance ........................................................ 13
AC Test Loads and Waveforms ..................................... 13
Switching Characteristics .............................................. 14
AC Timing Diagrams ...................................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 38-07127 Rev. *O
Page 3 of 23
CY7B993V/CY7B994V
RoboClock
®
Pinouts
Figure 1. 100-pin TQFP pinout
FBDS1
FBDS0
FBKB+
FBKA+
FBKB–
FBSEL
FBKA–
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
3F1
4F1
3F0
4F0
4DS1
3DS1
GND
4QB1
VCCN
4QB0
GND
GND
4QA1
VCCN
4QA0
GND
2DS1
1DS1
VCCQ
4DS0
3DS0
2DS0
1DS0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
2F0
FS
GND
2QA0
VCCN
2QA1
GND
GND
2QB0
VCCN
2QB1
GND
FBF0
1F0
GND
VCCQ
FBDIS
DIS4
DIS3
CY7B993/4V
GND
GND
GND
GND
GND
GND
GND
GND
VCCN
VCCN
OUTPUT_MODE
VCCQ
VCCQ
VCCQ
Document Number: 38-07127 Rev. *O
VCCQ
3QA0
3QA1
3QB0
3QB1
GND
2F1
1F1
INV3
DIS1
DIS2
VCCQ
VCCN
VCCN
VCCN
LOCK
QFA0
QFA1
1QB1
1QB0
1QA1
1QA0
GND
GND
GND
GND
GND
GND
GND
Page 4 of 23
CY7B993V/CY7B994V
RoboClock
®
Pinouts
(continued)
Figure 2. 100-pin BGA pinout
1
1QB1
2
1QB0
3
1QA1
4
1QA0
5
QFA0
6
QFA1
7
FBKB+
8
VCCQ
9
FBKA–
10
FBKA+
A
B
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCQ
FBKB–
FBSEL
REFA+
C
GND
GND
GND
GND
GND
GND
VCCQ
GND
GND
REFA–
D
LOCK
4F0
3F1
(3_level) (3_level)
4DS1
(3_level)
3DS1
(3_level)
GND
FBDS1 FBDS0
2F0
(3_level) (3_level) (3_level)
3F0
4F1
(3_level) (3_level)
VCCQ
REFSEL REFB–
E
4QB1
VCCN
GND
GND
FS
(3_level)
FBF0
(3_level)
VCCN
REFB+
F
4QB0
VCCN
GND
GND
GND
GND
VCCN
2QA0
G
4QA1
2DS1
(3_level)
VCCQ
GND
GND
GND
GND
VCCQ
1F0
(3_level)
2QA1
H
4QA0
1DS1
1DS0
(3_level) (3_level)
VCCQ
GND
GND
VCCQ
OUTPUT
MODE FBDIS
(3_level)
INV3
(3_level)
DIS3
2QB0
J
4DS0
3DS0
2DS0
(3_level) (3_level) (3_level)
2F1
1F1
(3_level) (3_level)
DIS1
VCCN
VCCN
GND
2QB1
K
DIS2
VCCN
3QA0
3QA1
GND
3QB0
3QB1
DIS4
Document Number: 38-07127 Rev. *O
Page 5 of 23
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