S2078TB datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> S2078TB

S2078TB: DescriptionTelecom Circuit, 2-Func, Bipolar, PBGA156, 21 X 21 MM, TBGA-156; CategoryWireless rf/communication Telecom circuit; File Size281KB，24 Pages; ManufacturerApplied Micro Circuits (MACOM)

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S2078TB Overview

Telecom Circuit, 2-Func, Bipolar, PBGA156, 21 X 21 MM, TBGA-156

S2078TB Parametric

Parameter Name	Attribute value
Maker	Applied Micro Circuits (MACOM)
Parts packaging code	BGA
package instruction	LBGA, BGA156,16X16,50
Contacts	156
Reach Compliance Code	unknown
JESD-30 code	S-PBGA-B156
length	21 mm
Number of functions	2
Number of terminals	156
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA156,16X16,50
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.65 mm
Maximum slew rate	500 mA
Nominal supply voltage	3.3 V
surface mount	YES
technology	BIPOLAR
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm

S2078TB Preview

DEVICE

SPECIFICATION

DUAL FIBRE CHANNEL TRANSCEIVER

GENERAL DESCRIPTION

S2078

FEATURES

• Functionally compliant with ANSI X3T11 Fibre

Channel physical and transmission protocol

standards

• 1062 MHz (Fibre Channel) operating rate

- Half rate operation

• Dual Transmitter incorporating phase-locked

loop (PLL) clock synthesis from low speed

reference

• Dual Receiver PLL provides clock and data

recovery

• Internally Series terminated TTL outputs

• Low-jitter serial PECL interface

• Local Loopback

• Interfaces with coax, twinax, or fiber optics

• Single +3.3V supply, 1.33 W power dissipation

• Compact 21mm x 21mm 156 TBGA package

The S2078 dual transmitter and receiver chip is de-

signed to provide two channels of high-speed serial

data transmission over fiber optic or copper interfaces

conforming to the requirements of the ANSI X3T11

Fibre Channel specification. The chip runs at 1062.5

Mbps serial data rate with an associated 10-bit paral-

lel data word. The chip provides two separate receive

PLLs which can be operated asyncronously.

Each bi-directional channel provides parallel-to-se-

rial and serial-to-parallel conversion, clock genera-

tion and recovery, and framing. The on-chip transmit

PLL synthesizes the high-speed clock from a low-

speed reference. The on-chip dual receive PLL is

used for clock recovery and data re-timing on the

two independent data inputs. The transmitter and re-

ceiver each support differential PECL-compatible I/O

for copper or fiber optic component interfaces and

provide excellent signal integrity. Local loopback

mode allows for system diagnostics. The chip re-

quires a 3.3V power supply and dissipates 1.33

watts.

Figure 1 shows the use of the S2062 and S2078 in a

Fibre Channel application. Figure 2 summarizes the

input/output signals of the device. Figures 3 and 4

show the transmit and receive block diagrams, re-

spectively.

APPLICATIONS

High-speed data communications

• Switched networks

• Data broadcast environments

• Fibre Channel Switches

Figure 1. Typical Dual Fibre Channel Application

FC INTERFACE

SERIAL BP DRIVER

DUAL

FIBRE

CHANNEL

INTERFACE

MAC

(ASIC)

TO SERIAL

BACKPLANE

S2078

MAC

(ASIC)

S2062

October 13, 2000 / Revision D

S2078

Figure 2. S2078 Input/Output Diagram

RESET

RATE

REFCLK

CLKSEL

TMODE

DUAL FIBRE CHANNEL TRANSCEIVER

TXAP/N

TCLKO

DINA[0:9]

TBCA

DINB[0:9]

TBCB

COM_DETA

DOUTA[0:9]

RBC1/0A

COM_DETB

DOUTB[0:9]

RBC1/0B

TXBP/N

RXAP/N

RXBP/N

TESTMODE

TESTMODE1

CMODE

LPEN

October 13, 2000 / Revision D

DUAL FIBRE CHANNEL TRANSCEIVER

Figure 3. Transmitter Block Diagram

S2078

RATE

REFCLK

CLKSEL

DIN PLL

10x/20x

REFCLK

TCLKO

TMODE

DINA[0:9]

FIFO

(input)

Shift

Reg

TXAP

TXAN

TXABP

0 1

TBCA

DINB[0:9]

FIFO

(input)

Shift

Reg

TXBP

TXBN

TXBBP

0 1

TBCB

October 13, 2000 / Revision D

S2078

Figure 4. Receiver Block Diagram

DUAL FIBRE CHANNEL TRANSCEIVER

TMODE

CMODE

RATE

REFCLK

RBC1/0A

COM_DETA

DOUTA[0:9]

TXABP

FIFO

(output)

DOUT CRU

Serial-

Parallel

RXAP

RXAN

RBC1/0B

COM_DETB

DOUTB[0:9]

TXBBP

FIFO

(output)

DOUT CRU

Serial-

Parallel

RXBP

RXBN

LPEN

October 13, 2000 / Revision D

DUAL FIBRE CHANNEL TRANSCEIVER

TRANSMITTER DESCRIPTION

The transmitter section of the S2078 contains a

single PLL which is used to generate the serial rate

transmit clock for all transmitters. Transmitter

functionalities shown schematically in Figure 3. Two

channels are provided with a variety of options re-

garding input clocking and loopback. The transmit-

ters operate at 1.062 GHz, 10 or 20 times the

reference clock frequency.

S2078

Data to be input to the S2078 should be coded to

insure transition density and DC balance. Data is input

to each channel of the S2078 as a 10 bit wide word. An

input FIFO and a clock input, TBCx, are provided for

each channel of the S2078. The device can operate in

two different modes. The S2078 can be configured to

use either the TBCx (TBC MODE) input or the

REFCLK input (REFCLK MODE). Table 2 provides a

summary of the input modes for the S2078.

Operation in the TBC MODE makes it easier for us-

ers to meet the relatively narrow setup and hold time

window required by the 106.25 Mbps 10 bit inter-

face. The TBC signal is used to clock the data into

an internal holding register and the S2078 synchro-

nizes its internal data flow to ensure stable opera-

tion. REFCLK, not TBCx, is used as the reference

for the transmit PLL. This ensures minimum jitter on

the high speed serial data stream.

The TBC must be frequency locked to REFCLK, but

may have an arbitrary but fixed phase relationship. Ad-

justment of internal timing of the S2078 is performed

during reset. Once synchronized, the S2078 can tolerate

up to

±3ns

of phase drift between TBC and REFCLK.

Figure 5 demonstrates the flexibility afforded by the

S2078. A low jitter reference is provided directly to

the S2078 at either 1/10 or 1/20 the serial data rate.

This insures minimum jitter in the synthesized clock

used for serial data transmission. A system clock

output at the parallel word rate, TCLKO, is derived

from the PLL and provided to the upstream circuit as

a system clock. This clock can be buffered as re-

quired without concern about added delay. There is

no phase requirement placed upon TCLKO and the

TBCx clock, which is provided back to the S2078,

Data Input

The S2078 has been designed to simplify the paral-

lel interface data transfer and provides flexibility in

the clocking of parallel data. Prior implementations

of this function have either forced the user to syn-

chronize transmit data to the reference clock or to

provide the output clock as a reference to the PLL,

resulting in increased jitter at the serial interface.

The S2078 incorporates a unique FIFO structure

which enables the user to provide a “clean” refer-

ence source for the PLL and to accept a separate

external clock which is used exclusively to reliably

clock data into the device.

The S2078 also provides a system clock output,

TCLKO, which is derived from the internal VCO. The

frequency of this output is constant at the parallel

word rate, 1/10 the serial data rate, regardless of

whether the reference is provided at 1/10 or 1/20 the

serial data rate. This clock can be used by upstream

circuitry as a system clock. See Table 1.

Table 1. Operating Rates

RATE

CLKSEL

REFCLK

Frequency

SDR/10

SDR/20

SDR/10

SDR/20

Serial Output

Rate

1062.5 Mbps

531.25 Mbps

TCLK0

Frequency

SDR/10

Figure 5. DIN Clocking with TBC

106.25 MHz or 53.125 MHz

REF

OSCILLATOR

Note: SDR = Serial Data Rate.

Table 2. Input Modes

TMODE

Operation

REFCLK

TCLKO

PLL

DINx[0:9]

REFCLK Mode. REFCLK used to clock data

into FIFOs for all channels.

TBC Mode. TBCx used to clock data into FIFOs

for all channels.

TBCx

Note that internal synchronization of FIFOs is performed upon

de-assertion of RESET.

MAC

ASIC

S2078

October 13, 2000 / Revision D

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