SRAM
Austin Semiconductor, Inc.
256K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
MT5C1005
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
FEATURES
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE\
OE\
Vss
•
•
•
•
32-Pin Flat Pack (F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
32-Pin LCC (ECW)
A9
A8
A7
NC
Vcc
A6
A5
4 3 2 1 31 32 30
A10
A11
A12
A13
A14
A15
A16
A17
CE\
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A2
A4
A3
A1
A0
NC
NC
NC
DQ4
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
14 15 16 17 18 19 20
DQ3
DQ2
DQ1
WE\
Vss
OE\
NC
• Package(s)
Ceramic DIP (400 mil)
C
Ceramic Quad LCC
(contact factory)
ECW
Ceramic LCC
EC
Ceramic Flatpack
F
Ceramic SOJ
DCJ
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
No. 109
No. 206
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
MT5C1005
A
A
A
ROW DECODER
A
A
A
A
A
A
A
DQ4
262,144 x 4-BIT
MEMORY ARRAY
I/O CONTROL
DQ1
CE\
COLUMN DECODER
OE\
WE\
A
A
A
A
A
A
A
A
POWER
DOWN
TRUTH TABLE
MODE
STANDBY
READ
READ
WRITE
OE\
X
L
H
X
CE\
H
L
L
L
WE\
X
H
H
L
DQ
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range (Vcc)................................-.5V to +7.0V
Storage Temperature......................................-65°C to +150°C
Voltage on any Pin Relative to Vss................-.5V to Vcc+.5V
Max Junction Temperature............................................+175°C
Lead Temperature (soldering 10 seconds)..................+260
o
C
Power Dissipation ...............................................................1 W
MT5C1005
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V<V
IN
<V
CC
Output(s) disabled
0V<V
OUT
<V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
CONDITIONS
SYM
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-10
-10
2.4
0.4
MAX
V
CC
+0.5
0.8
10
10
UNITS
V
V
µA
µA
V
V
1
1
NOTES
1
1
PARAMETER
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
WE\, CE\ < V
IL
; V
CC
= MAX
Output Open
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz*
SYM
I
cc
-20
180
MAX
-25
-35
180
180
-45
180
UNITS NOTES
mA
3
I
SBT2
25
25
25
25
mA
I
SBC
16
16
16
16
mA
* “L” version only.
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance (DQ1-DQ4)
CONDITIONS
V
IN
= 0V,
T
A
= 25°C, f = 1MHz
V
CC
= 5V
C
O
14
pF
4
SYM
C
I
MAX
12
UNITS
pF
NOTES
4
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C1005
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
20
20
20
3
3
10
0
20
8
0
8
20
15
15
0
0
15
12
0
3
0
25
20
20
0
0
20
15
0
3
0
0
10
35
30
30
0
0
30
20
0
3
0
0
25
10
0
20
45
35
35
0
0
35
25
0
3
0
3
3
12
0
35
20
0
25
25
25
25
3
3
20
0
45
25
35
35
35
3
3
25
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4
4
4, 6, 7
4, 6, 7
8
10
15
20
4, 6, 7
4, 6, 7
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
MT5C1005
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. Minimum of 5pF for t
EHQZ
, t
OHQZ
, t
ELQX
, t
OLQX
,
and t
WHQX
.
1.
2.
3.
7.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CE\ > (V
CC
-0.2V)
and
V
IN
> (V
CC
-0.2V)
or < 0.2V
CONDITIONS
SYM
V
DR
MIN
2
MAX
UNITS NOTES
V
Data Retention Current
V
CC
= 2V
I
CCDR
5
mA
Chip Deselect to Data
Retention Time
Operation Recovery Time
t
CDR
t
R
0
t
RC
--
ns
ns
4
4, 11
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
DATA RETENTION MODE
4.5V
CDR
V
DR
V
DR
> 2V
4.5V
t
R
CE\
V
IH
V
IL
MT5C1005
Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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