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74AUP1G0832GW,125

Description
74AUP1G0832 - Low-power 3-input AND-OR gate TSSOP 6-Pin
Categorylogic    logic   
File Size196KB,19 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74AUP1G0832GW,125 Overview

74AUP1G0832 - Low-power 3-input AND-OR gate TSSOP 6-Pin

74AUP1G0832GW,125 Parametric

Parameter NameAttribute value
Brand NameNXP Semiconductor
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeTSSOP
package instructionGREEN, PLASTIC, SC-88, SOT-363, SMT-6 PIN
Contacts6
Manufacturer packaging codeSOT363
Reach Compliance Codecompliant
seriesAUP/ULP/V
JESD-30 codeR-PDSO-G6
JESD-609 codee3
length2 mm
Load capacitance (CL)30 pF
Logic integrated circuit typeAND-OR GATE
MaximumI(ol)0.0017 A
Humidity sensitivity level1
Number of functions1
Number of entries3
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP6,.08
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply1.2/3.3 V
Prop。Delay @ Nom-Sup21.8 ns
propagation delay (tpd)21.8 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.2 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width1.25 mm
74AUP1G0832
Low-power 3-input AND-OR gate
Rev. 5 — 22 June 2012
Product data sheet
1. General description
The 74AUP1G0832 provides the Boolean function: Y = (A
×
B) + C. The user can choose
the logic functions OR, AND and AND-OR. All inputs can be connected to V
CC
or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
μA
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

74AUP1G0832GW,125 Related Products

74AUP1G0832GW,125 74AUP1G0832GM,115
Description 74AUP1G0832 - Low-power 3-input AND-OR gate TSSOP 6-Pin 74AUP1G0832 - Low-power 3-input AND-OR gate SON 6-Pin
Brand Name NXP Semiconductor NXP Semiconductor
Is it Rohs certified? conform to conform to
Parts packaging code TSSOP SON
package instruction GREEN, PLASTIC, SC-88, SOT-363, SMT-6 PIN 1 X 1.45 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-252, SOT-886, SON-6
Contacts 6 6
Manufacturer packaging code SOT363 SOT886
Reach Compliance Code compliant compliant
series AUP/ULP/V AUP/ULP/V
JESD-30 code R-PDSO-G6 R-PDSO-N6
JESD-609 code e3 e3
length 2 mm 1.45 mm
Load capacitance (CL) 30 pF 30 pF
Logic integrated circuit type AND-OR GATE AND-OR GATE
MaximumI(ol) 0.0017 A 0.0017 A
Humidity sensitivity level 1 1
Number of functions 1 1
Number of entries 3 3
Number of terminals 6 6
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP VSON
Encapsulate equivalent code TSSOP6,.08 SOLCC6,.04,20
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, VERY THIN PROFILE
method of packing TAPE AND REEL TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260
power supply 1.2/3.3 V 1.2/3.3 V
Prop。Delay @ Nom-Sup 21.8 ns 21.8 ns
propagation delay (tpd) 21.8 ns 21.8 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Maximum seat height 1.1 mm 0.5 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 0.8 V 0.8 V
Nominal supply voltage (Vsup) 1.2 V 1.1 V
surface mount YES YES
technology CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE
Terminal surface Tin (Sn) Tin (Sn)
Terminal form GULL WING NO LEAD
Terminal pitch 0.65 mm 0.5 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
width 1.25 mm 1 mm
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