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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 8440259EKI-45LFT
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8440259EKI-45LFT

Description
VFQFPN-32, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1MB，21 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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8440259EKI-45LFT Overview

VFQFPN-32, Reel

8440259EKI-45LFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionHVQCCN, LCC32,.2SQ,20
Contacts32
Manufacturer packaging codeNLG32P1
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeS-XQCC-N32
JESD-609 codee3
length5 mm
Humidity sensitivity level3
Number of terminals32
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency156.25 MHz
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC32,.2SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency25 MHz
Certification statusNot Qualified
Maximum seat height1 mm
Maximum slew rate105 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width5 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER

8440259EKI-45LFT Preview

FemtoClock
®
Crystal/LVCMOS-to-
LVDS/LVCMOS Frequency Synthesizer
ICS8440259I-45
DATA SHEET
General Description
The ICS8440259I-45 is a nine output synthesizer optimized to
generate Gigabit and 10 Gigabit Ethernet clocks. Using a 25MHz,
18pF parallel resonant crystal, the device will generate 156.25MHz,
125MHz and 3.90625MHz clocks with mixed LVDS and LVCMOS/
LVTTL output levels. The ICS8440259I-45 uses IDT’s 3
RD
generation
low phase noise VCO technology and can achieve <1ps typical rms
phase jitter, easily meeting Ethernet jitter requirements. The
ICS8440259I-45 is packaged in a small, 5mm x 5mm VFQFN
package that is optimum for applications with space limitations.
Features
•
One differential LVDS output at 156.25MHz or 125MHz
Four differential LVDS outputs at 125MHz
Three LVCMOS/LVTTL single-ended outputs at 125MHz
One LVCMOS/LVTTL single-ended output at 3.90625MHz
•
•
•
•
•
•
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
VCO range: 560MHz - 690MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical), LVDS outputs
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical), Q0, nQ0 output
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
nPLL_BYPASS
Pullup
F_SEL
Pulldown
REF_CLK
Pulldown
25MHz
0
0
Q0
nQ0
XTAL_IN
Phase
Detector
1
VCO
560-690MHz
÷5
÷4
1
OSC
XTAL_OUT
0
Q1
nQ1
Q2
nQ2
Q3
÷5
1
Pin Assignment
XTAL_OUT
REF_CLK
XTAL_IN
F_SEL
nPLL_BYPASS
GND
÷25
V
DDA
V
DD
nQ3
Q4
Q8
V
DDO_LVCMOS
Q7
GND
Q6
V
DDO_LVCMOS
Q5
GND
Q7
Q6
Q5
nQ4
32 31 30 29 28 27 26 25
Q0
nQ0
GND
Q1
nQ1
V
DDO_LVDS
Q2
nQ2
1
2
3
4
5
6
7
8
9
GND
24
ICS8440259I-45
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
10 11 12 13 14 15 16
nQ4
GND
V
DDO_LVDS
nQ3
V
DD
Q3
Q4
23
22
21
20
19
18
17
÷32
Q8
ICS8440259EKI-45 REVISION A FEBRUARY25, 2011
1
©2011 Integrated Device Technology, Inc.
ICS8440259I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
3, 9, 15,
17, 21, 32
4, 5
6, 12
7, 8
10, 11
13, 14
16, 27
18, 20, 22, 24
19, 23
25
26
28
29
30,
31
Name
Q0, nQ0
GND
Q1, nQ1
V
DDO_LVDS
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
DD
Q5, Q6, Q7, Q8
V
DDO_LVCMOS
V
DDA
nPLL_BYPASS
F_SEL
REF_CLK
XTAL_IN,
XTAL_OUT
Output
Power
Output
Power
Output
Output
Output
Power
Output
Power
Power
Input
Input
Input
Input
Pullup
Pulldown
Pulldown
Type
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Output supply pins for Q[0:4], nQ[0:4] LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Single-ended clock outputs.LVCMOS/LVTTL interface levels.
Output supply pins for Q[5:8] LVCMOS outputs.
Analog supply pin.
Input select and PLL bypass control pin. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Q[5:8]
V
DDO_LVCMOS
= 3.3V
Q[5:8]
V
DDO_LVCMOS
= 3.465V
Test Conditions
Minimum
Typical
4
8
51
51
20
Maximum
Units
pF
pF
k
Ω
k
Ω
Ω
ICS8440259EKI-45 REVISION A FEBRUARY25, 2011
2
©2011 Integrated Device Technology, Inc.
ICS8440259I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Function Tables
Table 3A. F_SEL Frequency Select Function Table
Input
F_SEL
0
1
Output Divider Value
÷5
÷4
Output Frequency
Q0, nQ0 (MHz)
125 (default)
156.25
Table 3B. PLL Bypass and Input Select Function Table
Inputs
nPLL_BYPASS
0
1
PLL BYPASS
PLL Bypassed
PLL Enabled
Input Selected
REF_CLK
XTAL_IN, XTAL_OUT (default)
ICS8440259EKI-45 REVISION A FEBRUARY25, 2011
3
©2011 Integrated Device Technology, Inc.
ICS8440259I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_LVCMOS
+ 0.5V
10mA
15mA
-40°C to +85°C
37°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_LVCMOS
= V
DDO_LVDS
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Test Conditions
Minimum
3.135
V
DD
– 0.35
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
105
35
4
77
Units
V
V
V
mA
mA
mA
mA
V
DDO_LVCMOS,
Output Supply Voltage
V
DDO_LVDS
I
DD
I
DDA
I
DDO_LVCMOS
I
DDO_LVDS
Power Supply Current
Analog Supply Current
LVCMOS Output Supply Current
LVDS Output Supply Current
ICS8440259EKI-45 REVISION A FEBRUARY25, 2011
4
©2011 Integrated Device Technology, Inc.
ICS8440259I-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO_LVCMOS
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
Output
High Voltage
Output
Low Voltage
REF_CLK, F_SEL
nPLL_BYPASS
REF_CLK, F_SEL
nPLL_BYPASS
Q[5:8]
Q[5:8]
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
I
IL
V
OH
V
OL
I
OH
= -12mA
I
OL
= 12mA
Table 4C. LVDS DC Characteristics,
V
DD
= V
DDO_LVDS
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.20
Test Conditions
Minimum
250
Typical
Maximum
520
50
1.55
50
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
Ω
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS8440259EKI-45 REVISION A FEBRUARY25, 2011
5
©2011 Integrated Device Technology, Inc.
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