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SST89V54RD-33-I-PIE

Description
Microcontroller, 8-Bit, FLASH, 8051 CPU, 33MHz, CMOS, PDIP40, ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size935KB,81 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

SST89V54RD-33-I-PIE Overview

Microcontroller, 8-Bit, FLASH, 8051 CPU, 33MHz, CMOS, PDIP40, ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40

SST89V54RD-33-I-PIE Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Parts packaging codeDIP
package instructionDIP, DIP40,.6
Contacts40
Reach Compliance Codeunknown
ECCN code3A991.A.2
Has ADCNO
Address bus width16
bit size8
CPU series8051
maximum clock frequency33 MHz
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeR-PDIP-T40
JESD-609 codee3
length51.943 mm
Number of I/O lines32
Number of terminals40
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP40,.6
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)260
power supply3/3.3 V
Certification statusNot Qualified
RAM (bytes)1024
rom(word)16384
ROM programmabilityFLASH
Maximum seat height5.588 mm
speed33 MHz
Maximum slew rate47 mA
Maximum supply voltage3.6 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width15.24 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
SST89E/V58 / 54 / 52RD2/RD FlashFlex51 MCU
Data Sheet
FEATURES:
• 8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• SST89E5xRD2 Operation
– 0 to 40 MHz at 5V
• SST89V5xRD2 Operation
– 0 to 33 MHz at 3V
• 1 KByte Internal RAM
• Dual Block SuperFlash EEPROM
– 8/16/32 KByte primary block +
8 KByte secondary block
(128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High-Current Drive Ports (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins) and
One 4-bit Port
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
• Packages Available
– 40-contact WQFN (Port 4 feature not available)
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E5xRD2/RD and SST89V5xRD2/RD are
members of the FlashFlex51 family of 8-bit microcontroller
products designed and manufactured with SST’s patented
and proprietary SuperFlash CMOS semiconductor pro-
cess technology. The split-gate cell design and thick-oxide
tunneling injector offer significant cost and reliability bene-
fits for SST’s customers. The devices use the 8051 instruc-
tion set and are pin-for-pin compatible with standard 8051
microcontroller devices.
The devices come with 16/24/40 KByte of on-chip flash
EEPROM program memory which is partitioned into 2
independent program memory blocks. The primary Block 0
occupies 8/16/32 KByte of internal program memory space
and the secondary Block 1 occupies 8 KByte of internal
program memory space.
The 8-KByte secondary block can be mapped to the lowest
location of the 8/16/32 KByte address space; it can also be
hidden from the program counter and used as an indepen-
dent EEPROM-like data memory.
In addition to the 16/24/40 KByte of EEPROM program
memory on-chip, the devices can address up to 64 KByte
of external program memory. In addition to 1024 x8 bits of
on-chip RAM, up to 64 KByte of external RAM can be
addressed.
The flash memory blocks can be programmed via a stan-
dard 87C5x OTP EPROM programmer fitted with a special
adapter and the firmware for SST’s devices. During power-
on reset, the devices can be configured as either a slave to
an external host for source code storage or a master to an
external host for an in-application programming (IAP) oper-
ation. The devices are designed to be programmed in-sys-
tem and in-application on the printed circuit board for
maximum flexibility. The devices are pre-programmed with
an example of the bootstrap loader in the memory, demon-
strating the initial user program code loading or subsequent
user code updating via the IAP operation. The sample
bootstrap loader is available for the user’s reference and
convenience only; SST does not guarantee its functionality
or usefulness. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
©2006 Silicon Storage Technology, Inc.
S71255-05-000
5/06
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
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