HMS9xC7132 / HMS9xC7134
1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
13.2 Watchdog timer overflow . . . . . . . . . . . . . . . . . . . 37
13.3 Low VDD voltage reset . . . . . . . . . . . . . . . . . . . . 37
2. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . 2
3. PIN ASSIGNMENT . . . . . . . . . . . . . . . . . 3
3.1 40PDIP pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3.2 42SDIP pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
14. WATCHDOG TIMER . . . . . . . . . . . . . . 38
15. TIMER . . . . . . . . . . . . . . . . . . . . . . . . . 39
15.1 Timer0 and Timer1 . . . . . . . . . . . . . . . . . . . . . . . 39
15.2 TIMER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16. DDC INTERFACE . . . . . . . . . . . . . . . . 42
16.1 The SFRs for DDC Interface . . . . . . . . . . . . . . . . 43
16.2 DDC1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
16.3 DDC2B protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 46
16.4 DDC2AB/DDC2B+ protocol . . . . . . . . . . . . . . . . . 47
16.5 The RAM Buffer and DDC application . . . . . . . . . 48
4. PACKAGE DIMENSIONS . . . . . . . . . . . . 5
4.1 40 PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.2 42 SDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
5. PIN FUNCTION . . . . . . . . . . . . . . . . . . . . 6
5.1 40DIP Pin Description . . . . . . . . . . . . . . . . . . . . . . .7
5.2 42SDIP Pin Description . . . . . . . . . . . . . . . . . . . . . .8
17. I2C INTERFACE . . . . . . . . . . . . . . . . . 51
17.1 The SFRs for I2C Interface . . . . . . . . . . . . . . . . . 52
17.2 Programmer’s Guide for I2C and DDC2 . . . . . . . 54
6. PORT STRUCTURES . . . . . . . . . . . . . . . 9
7. ELECTRICAL CHARACTERISTICS . . . 11
7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .11
7.2 Recommended Operating Conditions . . . . . . . . . .11
7.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . .11
7.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13
18. PULSE WIDTH MODULATION . . . . . . 57
18.1 Static PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
18.2 Dynamic PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
19. SYNC PROCESSOR . . . . . . . . . . . . . . 60
19.1 Sync input signals . . . . . . . . . . . . . . . . . . . . . . . . 60
19.2 Horizontal polarity correction . . . . . . . . . . . . . . . . 60
19.3 Vertical polarity correction . . . . . . . . . . . . . . . . . . 60
19.4 Vertical sync separation . . . . . . . . . . . . . . . . . . . . 60
19.5 Horizontal sync. detection . . . . . . . . . . . . . . . . . . 62
19.6 Vertical sync. detection . . . . . . . . . . . . . . . . . . . . 62
19.7 Horizontal sync. generator . . . . . . . . . . . . . . . . . . 65
19.8 Vertical sync. generator . . . . . . . . . . . . . . . . . . . . 66
19.9 HSYNC / VSYNC output driver . . . . . . . . . . . . . . 66
19.10 Clamp pulse generator . . . . . . . . . . . . . . . . . . . 67
19.11 Pattern generator . . . . . . . . . . . . . . . . . . . . . . . . 67
19.12 Suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8. MEMORY ORGANIZATION . . . . . . . . . 16
8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
8.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . .17
8.3 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8.4 List of SFRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8.5 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . .22
9. INTERRUPTS . . . . . . . . . . . . . . . . . . . . 24
9.1 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . .24
9.2 Interrupt Enable structure . . . . . . . . . . . . . . . . . . .26
9.3 Interrupt Priority structure . . . . . . . . . . . . . . . . . . .27
9.4 How Interrupt are handled . . . . . . . . . . . . . . . . . . .29
10. POWER-SAVING MODE . . . . . . . . . . . 30
10.1 Power control register . . . . . . . . . . . . . . . . . . . . .30
10.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
10.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . .31
20. AD-CONVERTOR (ADC) . . . . . . . . . . . 71
21. OPERATION MODE . . . . . . . . . . . . . . 73
21.1 OTP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
21.2 64MQFP pinning and Package Dimensions . . . . 78
21.3 64MQFP Pin Description . . . . . . . . . . . . . . . . . . . 79
21.4 Development Tools . . . . . . . . . . . . . . . . . . . . . . . 81
11. I/O PORTS . . . . . . . . . . . . . . . . . . . . . . 32
11.1 Pin function selection . . . . . . . . . . . . . . . . . . . . . .33
12. OSCIALLTOR . . . . . . . . . . . . . . . . . . . 36
13. RESET . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
22. INSTRUCTION SET . . . . . . . . . . . . . . . 82
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
HMS9xC7132 / HMS9xC7134
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
FOR MONITOR
1. OVERVIEW
1.1 Description
The HMS9xC7132/4 is a single-chip microcontroller of the 80C51 family, which is dedicated for monitor application. It is particularly
suitable for multi-sync computer monitor controller. This contains DDC interfaces to the PC host, sync-detector and sync-processor for
auto-sync application, ADC, static PWM, dynamic PWM and I
2
C bus interface for control of the video and deflection functions of the
monitor.
Device name
HMS91C7132/4
ROM Size
32K bytes
Mask ROM
RAM
Size
512 bytes
I/O
30(42DIP)
32(42SDIP)
OTP
HMS97C7132/4
Package
40DIP(HMS91C7132/4),
42SDIP(HMS91C7132/4K)
1.2 Features
• 80C51 core
• 32K bytes of ROM for HMS91C7132/4
(32K bytes of OTP ROM for HMS97C7132/4)
• 256 bytes of RAM and 256 bytes of XRAM for
DDC operation
• Uses an external crystal of 12 MHz
• One DDC compliant interface :
-
Fully supports DDC1 with dedicated hardware
- DDC2B, DDC2AB and DDC2B+ compliant dedi-
cated hardware based on an I
2
C bus interface
- RAM buffer with programmable size, 128 bytes
or 256 bytes, which can be used for DDC opera-
tion or shared as system RAM
• On-chip sync processor
-
HSYNC frequency with 12-bit resolution
- VSYNC frequency with 12-bit resolution
- HSYNC and VSYNC polarity
- HSYNC and VSYNC presence detection
- Composite sync separation
- Free running sync. generation
- Clamping pulse output
- Pattern generation
- Separate input for a SOG signal
- Missing pulse insertion option
- HSYNC/ VSYNC change interrupt
• One multi-master/slave I2C interface (up to
400K bit/s) for control of other system IC’s
• Eight 8-bit Static PWM outputs for digital con-
trol applications
• Two 8-bit Dynamic PWM outputs for various
waveform generation
• One 8-bit ADC with 4 input channels
• LED driver port ; two port lines with
15 mA drive capability
• One 8-bit port only for I/O function
• 24 derivative I/O ports configurable for alterna-
tive functions
• Watchdog timer (524ms max.)
• On-chip low VDD voltage detect and reset
(reset period: 524ms)
• Operating temperature : 0
to 70
• Special idle and power-down modes with low
power consumption
• Single power supply : 4.5V to 5.5V
May.2001 ver1.1
1
京公网安备 11010802033920号
EEWORLD
