240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb B ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb B ver. DDR2 SDRAMs in Fine Ball
Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb B ver. based DDR2 Unbuffered
DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
All inputs and outputs are compatible with SSTL_1.8
interface
4 Bank architecture
Posted CAS
Programmable CAS Latency 3 , 4 , 5, 6
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
•
•
•
•
•
•
•
•
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
Auto refresh and self refresh supported
Partial Array Self Refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA(64Mx8), 84ball
FBGA(32Mx16)
133.35 x 30.00 mm form factor
Lead-free Products are RoHS compliant
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ORDERING INFORMATION
Part Name
HYMP532U64BP6-E3/C4/Y5
HYMP564U64BP8-E3/C4/Y5/S5/S6
HYMP564U72BP8-E3/C4/Y5/S5
HYMP512U64BP8-E3/C4/Y5/S5/S6
HYMP512U72BP8-E3/C4/Y5/S5
Density
256MB
512MB
512MB
1GB
1GB
Organization
32Mx64
64Mx64
64Mx72
128Mx64
128Mx72
# of
DRAMs
4
8
9
16
18
# of
ranks
1
1
1
2
2
Materials
Lead free
Lead free
Lead free
Lead free
Lead free
ECC
None
None
ECC
None
ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6 / Feb. 2007
1
1240pin
DDR2 SDRAM Unbuffered DIMMs
SPEED GRADE & KEY PARAMETERS
E3
(DDR2-400)
Speed @CL3
Speed @CL4
Speed @CL5
Speed @CL6
CL-tRCD-tRP
400
400
400
-
3-3-3
C4
(DDR2-533)
400
533
533
-
4-4-4
Y5
(DDR2-667)
400
533
667
-
5-5-5
S5
(DDR2-800)
400
533
800
-
5-5-5
S6
(DDR2-800)
-
533
667
800
6-6-6
Unit
Mbps
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization Ranks
SDRAMs
# of
DRAMs
4
8
9
16
18
# of row/bank/column Address
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
256MB
512MB
512MB
1GB
1GB
32M x 64
64M x 64
64M x 72
128M x 64
128M x 72
1
1
1
2
2
32Mb x 16
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
Rev. 0.6 / Feb. 2007
2
1240pin
DDR2 SDRAM Unbuffered DIMMs
Input/Output Functional Description
Symbol
CK[2:0], CK[2:0]
Type
SSTL
Polarity
Differential
Crossing
Pin Description
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are
sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read)
data is reference to the crossing of CK and /CK (Both directions of crossing)
CKE[1:0]
SSTL
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
Active High low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Active Low
Active Low
Active High
Enables the associated DDR2 SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity.
For all current DDR2 unbuffered DIMM designs, V
DDQ
shares the same power plane as
V
DD
pins.
-
Selects which DDR2 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, Address input difines the row
address(RA0~RA15)
During a Read or Write command cycle, Address input defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to
the column address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-
mand cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to pre-
charge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
S[1:0]
RAS, CAS, WE
ODT[1:0]
Vref
V
DDQ
BA[2:0]
SSTL
SSTL
SSTL
Supply
Supply
SSTL
A[9:0], A10/AP,
A[13:11]
SSTL
-
DQ[63:0],
CB[7:0]
DM[8:0]
SSTL
-
SSTL
DM is an input mask signal for write data. Input data is masked when DM is sampled High
coincident with that input data during a write access. DM is sampled on both edges of
Active High
DQS. Although DM pins are input only, the DM loading matches the DQ and DQS load-
ing.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins are tied to V
DD
/V
DDQ
planes on these modules.
Differential
crossing
-
-
-
Data strobe for input and output data. For Rawcards using x16 organized DRAMs,
DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of
the DRAM
These signals are tied at the system planar to either V
SS
or V
DD
to configure the serial
SPD EEPROM.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to V
DD
to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to V
DD
to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power
plane. EEPROM supply is operable from 1.7V to 3.6V.
V
DD
,V
SS
DQS[8:0],
DQS[8:0]
SA[2:0]
SDA
SCL
VDDSPD
Supply
SSTL
Supply
Rev. 0.6 / Feb. 2007
3
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