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Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> ADM483EAR-REEL
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ADM483EAR-REEL

Description
LINE TRANSCEIVER, PDSO8, SOIC-8
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size1MB，17 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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ADM483EAR-REEL Overview

LINE TRANSCEIVER, PDSO8, SOIC-8

ADM483EAR-REEL Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
MakerRochester Electronics
Parts packaging codeSOIC
package instructionSOIC-8
Contacts8
Reach Compliance Codeunknown
Differential outputYES
Number of drives1
Input propertiesDIFFERENTIAL SCHMITT TRIGGER
Interface integrated circuit typeLINE TRANSCEIVER
Interface standardsEIA-422; EIA-485
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.9 mm
Humidity sensitivity level1
Number of functions1
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)240
Maximum receive delay2000 ns
Number of receiver bits1
Maximum seat height1.75 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyBICMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
maximum transmission delay2000 ns
width3.9 mm

ADM483EAR-REEL Preview

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±15 kV ESD Protected, Slew Rate
Limited, 5 V, RS-485 Transceiver
ADM483E
FEATURES
±15 kV ESD protection
250 kbps data rate
Reduced slew rate for low EM interference
Single 5 V ± 10% supply
−7 V to +12 V bus common-mode range
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Short-circuit protection
36 μA supply current
0.1 μA shutdown current
FUNCTIONAL BLOCK DIAGRAM
ADM483E
RO
RE
DE
DI
D
R
B
A
06012-001
Figure 1.
APPLICATIONS
Low power RS-485 systems
Electrically harsh environments
EMI sensitive applications
DTE-DCE interface
Packet switching
Local area networks
GENERAL DESCRIPTION
The ADM483E is a 5 V, low power data transceiver with ±15 kV
ESD protection suitable for half-duplex communication on
multipoint bus transmission lines. The ADM483E is designed
for balanced data transmission and complies with TIA/EIA
Standards RS-485 and RS-422, which allow up to 32 transceivers
on a bus.
The ADM483E has a low current shutdown mode in which it
consumes only 0.1 μA.
Because only one driver is enabled at any time, the output of a
disabled or power-down driver is three-stated to avoid
overloading the bus.
Drivers are short-circuit current-limited and are protected
against excessive power dissipation by thermal shutdown
circuitry that places their outputs into a high impedance state.
The receiver input has a fail-safe feature that guarantees a logic
high output if the input is open circuit.
The ADM483E is fully specified over the industrial temperature
ranges and is available in 8-lead SOIC_N packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1997–2007 Analog Devices, Inc. All rights reserved.
ADM483E
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits and Switching Characteristics...................................9
General Information ...................................................................... 11
ESD Transient Protection Scheme ........................................... 11
ESD Testing ................................................................................. 12
Applications Information .............................................................. 13
Differential Data Transmission ................................................ 13
Cable and Data Rate................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
12/07—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features ......................................................................... 1
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 5............................................................................ 6
Changes to Typical Performance Characteristics Section........... 7
Changes to Test Circuits and Switching Characteristics Section...9
Changes to General Information Section.................................... 11
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
1/97—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADM483E
SPECIFICATIONS
V
CC
= 5 V ± 10%. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DRIVER
Differential Output Voltage, V
OD
Min
Typ
Max
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
±1.0
−0.2
70
12
1
−0.8
Logic Enable Input Current (RE)
CMOS Output Voltage Low, V
OL
CMOS Output Voltage High, V
OH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
I
CC
Supply Current in Shutdown
ESD IMMUNITY
ESD Protection
±1
0.4
4.0
7
85
±2.0
36
270
0.1
±15
120
360
10
+0.2
Unit
V
V
V
V
V
V
V
mA
mA
V
V
μA
V
mV
kΩ
mA
mA
μA
V
V
mA
μA
μA
μA
μA
kV
Test Conditions/Comments
V
CC
= 5.25 V; R = ∞, see Figure 15
R = 50 Ω (RS-422), see Figure 15
R = 27 Ω (RS-485), see Figure 15
V
IN
= –7 V to +12 V
R = 27 Ω or 50 Ω, see Figure 15
R = 27 Ω or 50 Ω, see Figure 15
R = 27 Ω or 50 Ω
–7 V ≤ V
O
≤ +12 V
–7 V ≤ V
O
≤ +12 V
2.0
1.5
1.5
Δ|V
OD
| for Complementary Output States
Common-Mode Output Voltage, V
OC
Δ|V
OC
| for Complementary Output States
Output Short-Circuit Current (V
OUT
= High)
Output Short-Circuit Current (V
OUT
= Low)
CMOS Input Logic Threshold Low, V
INL
CMOS Input Logic Threshold High, V
INH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, V
TH
Input Voltage Hysteresis, ΔV
TH
Input Resistance
Input Current (A, B)
2.0
1.4
1.4
−7 V ≤ V
CM
≤ +12 V
V
CM
= 0 V
−7 V ≤ V
CM
≤ +12 V
V
IN
= 12 V
V
IN
= –7 V
I
OUT
= 4.0 mA
I
OUT
= −4.0 mA
V
OUT
= GND or V
CC
0.4 V ≤ V
OUT
≤ 2.4 V
Outputs unloaded, receivers enabled
DE = 0 V (disabled), RE = 0 V
DE = 5 V (enabled), RE = 0 V
DE = 0 V, RE = V
CC
HBM air discharge; Pin A, Pin B
Rev. A | Page 3 of 16
ADM483E
TIMING SPECIFICATIONS
V
CC
= 5 V ± 10%. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
DRIVER
Propagation Delay Input to Output (t
PLH
, t
PHL
)
Driver Output to Output (t
SKEW
)
Driver Rise/Fall Time (t
R
, t
F
)
Driver Enable to Output Valid
Driver Disable Timing
RECEIVER
Propagation Delay Input to Output (t
PLH
, t
PHL
)
Skew (|t
PLH
– t
PHL
|)
Receiver Enable (t
EN1
)
Receiver Disable (t
EN2
)
SHUTDOWN
Time to Shutdown
Driver Enable from Shutdown
Receiver Enable from Shutdown
250
250
300
250
200
10
10
50
200
Min
250
100
Typ
Max
2000
800
2000
2000
3000
2000
50
50
3000
5000
5000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
R
L
Diff = 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 16 and
Figure 17
R
L
Diff = 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 16 and
Figure 17
R
L
Diff = 54 Ω, C
L1
= C
L2
= 100 pF, see Figure 16 and
Figure 17
R
L
= 500 Ω, C
L
= 100 pF, see Figure 18 and Figure 19
R
L
= 500 Ω, C
L
= 15 pF, see Figure 18 and Figure 19
C
L
= 15 pF, see Figure 20
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 22
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 22
R
L
= 500 Ω, C
L
= 100 pF, see Figure 18 and Figure 19
R
L
= 1 kΩ, C
L
= 15 pF, see Figure 22
Rev. A | Page 4 of 16
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ADM483EAR-REEL Related Products

ADM483EAR-REEL ADM483EARZ-REEL ADM483EAR ADM483EARZ
Description LINE TRANSCEIVER, PDSO8, SOIC-8 LINE TRANSCEIVER, PDSO8, SOIC-8 LINE TRANSCEIVER, PDSO8, SOIC-8 LINE TRANSCEIVER, PDSO8, SOIC-8
Is it lead-free? Contains lead Lead free Contains lead Lead free
Maker Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics
Parts packaging code SOIC SOIC SOIC SOIC
package instruction SOIC-8 SOIC-8 SOIC-8 SOIC-8
Contacts 8 8 8 8
Reach Compliance Code unknown unknown unknown unknown
Differential output YES YES YES YES
Number of drives 1 1 1 1
Input properties DIFFERENTIAL SCHMITT TRIGGER DIFFERENTIAL SCHMITT TRIGGER DIFFERENTIAL SCHMITT TRIGGER DIFFERENTIAL SCHMITT TRIGGER
Interface integrated circuit type LINE TRANSCEIVER LINE TRANSCEIVER LINE TRANSCEIVER LINE TRANSCEIVER
Interface standards EIA-422; EIA-485 EIA-422; EIA-485 EIA-422; EIA-485 EIA-422; EIA-485
JESD-30 code R-PDSO-G8 R-PDSO-G8 R-PDSO-G8 R-PDSO-G8
JESD-609 code e0 e3 e0 e3
length 4.9 mm 4.9 mm 4.9 mm 4.9 mm
Humidity sensitivity level 1 1 NOT APPLICABLE 1
Number of functions 1 1 1 1
Number of terminals 8 8 8 8
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP SOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) 240 260 240 260
Maximum receive delay 2000 ns 2000 ns 2000 ns 2000 ns
Number of receiver bits 1 1 1 1
Maximum seat height 1.75 mm 1.75 mm 1.75 mm 1.75 mm
Maximum supply voltage 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage 5 V 5 V 5 V 5 V
surface mount YES YES YES YES
technology BICMOS BICMOS BICMOS BICMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface TIN LEAD MATTE TIN TIN LEAD MATTE TIN
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 40 30 40
maximum transmission delay 2000 ns 2000 ns 2000 ns 2000 ns
width 3.9 mm 3.9 mm 3.9 mm 3.9 mm

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