MPC8347ZUAJDA datasheet, PDF - EEWORLD Datasheet

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MPC8347ZUAJDA: Description32-BIT, 533MHz, MICROPROCESSOR, PBGA672, 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，120 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC8347ZUAJDA Overview

32-BIT, 533MHz, MICROPROCESSOR, PBGA672, 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672

MPC8347ZUAJDA Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	LBGA,
Contacts	672
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	ALSO REQUIRES 2.5V AND 3.3V SUPPLY
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	66 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B672
length	35 mm
low power mode	YES
Number of terminals	672
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Certification status	Not Qualified
Maximum seat height	1.69 mm
speed	533 MHz
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Freescale Semiconductor

Technical Data

MPC8347EAEC

Rev. 2, 8/2006

MPC8347EA PowerQUICC™ II Pro

Integrated Host Processor Hardware

Specifications

The MPC8347EA contains a PowerPC™ processor core

(built on Power Architecture™ technology) with system

logic for networking, storage, and general-purpose

embedded applications. For functional characteristics of the

processor, refer to the

MPC8349EA PowerQUICC™ II Pro

Integrated Host Processor Reference Manual,

Rev. 0.

To locate published errata or updates for this document,

contact your Freescale sales office.

NOTE

The information in this document is accurate

for revision 3.0 silicon and later. For

information on revision 1.1 silicon and earlier

versions, see the

MPC8347E

PowerQUICC™ II Pro Integrated Host

Processor Hardware Specifications.

See

Section 23.1, “Part Numbers Fully

Addressed by this Document,”

for silicon

revision level determination.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Ethernet: Three-Speed Ethernet, MII Management . 29

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 70

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

System Design Information . . . . . . . . . . . . . . . . . . 111

Document Revision History . . . . . . . . . . . . . . . . . . 117

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 117

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